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Subject[PATCH v3 2/2] x86/kvm: Implement MSR_HWCR support
Date
From: Borislav Petkov <bp@suse.de>

The hardware configuration register has some useful bits which can be
used by guests. Implement McStatusWrEn which can be used by guests when
injecting MCEs with the in-kernel mce-inject module.

For that, we need to set bit 18 - McStatusWrEn - first, before writing
the MCi_STATUS registers (otherwise we #GP).

Add the required machinery to do so.

Signed-off-by: Borislav Petkov <bp@suse.de>
Tested-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
arch/x86/kvm/svm.c | 12 +++++++++---
arch/x86/kvm/x86.c | 34 +++++++++++++++++++++++++++++++---
2 files changed, 40 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 5c9c26dc7d84..db8e943f7576 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -251,6 +251,9 @@ struct vcpu_svm {

/* which host CPU was used for running this vcpu */
unsigned int last_cpu;
+
+ /* MSRC001_0015 Hardware Configuration */
+ u64 msr_hwcr;
};

/*
@@ -4155,7 +4158,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
msr_info->data = svm->msr_decfg;
break;
case MSR_K7_HWCR:
- msr_info->data = 0;
+ msr_info->data = svm->msr_hwcr;
break;
default:
return kvm_get_msr_common(vcpu, msr_info);
@@ -4365,8 +4368,11 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
data &= ~(u64)0x40; /* ignore flush filter disable */
data &= ~(u64)0x100; /* ignore ignne emulation enable */
data &= ~(u64)0x8; /* ignore TLB cache disable */
- data &= ~(u64)0x40000; /* ignore Mc status write enable */
- if (data != 0) {
+
+ /* Handle McStatusWrEn */
+ if (data == BIT_ULL(18)) {
+ svm->msr_hwcr = data;
+ } else if (data != 0) {
vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
data);
return 1;
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index d9abbe24deb5..607fe883113c 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -2262,6 +2262,30 @@ static void kvmclock_sync_fn(struct work_struct *work)
KVMCLOCK_SYNC_PERIOD);
}

+/*
+ * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
+ */
+static bool __set_mci_status(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
+{
+ if (guest_cpuid_is_amd(vcpu)) {
+ struct msr_data tmp;
+
+ tmp.index = MSR_K7_HWCR;
+
+ if (kvm_x86_ops->get_msr(vcpu, &tmp))
+ return false;
+
+ /* McStatusWrEn enabled? */
+ if (tmp.data & BIT_ULL(18))
+ return true;
+ }
+
+ if (msr_info->data != 0)
+ return false;
+
+ return true;
+}
+
static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
{
u64 mcg_cap = vcpu->arch.mcg_cap;
@@ -2293,9 +2317,13 @@ static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
if ((offset & 0x3) == 0 &&
data != 0 && (data | (1 << 10)) != ~(u64)0)
return -1;
- if (!msr_info->host_initiated &&
- (offset & 0x3) == 1 && data != 0)
- return -1;
+
+ /* MCi_STATUS */
+ if ((offset & 0x3) == 1 && !msr_info->host_initiated) {
+ if (!__set_mci_status(vcpu, msr_info))
+ return -1;
+ }
+
vcpu->arch.mce_banks[offset] = data;
break;
}
--
2.19.1
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