lkml.org 
[lkml]   [2018]   [Nov]   [14]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
SubjectRE: [PATCH v7 11/13] arch/x86: Introduce QOS feature for AMD
Date
Fenghua,

> -----Original Message-----
> From: linux-kernel-owner@vger.kernel.org <linux-kernel-
> owner@vger.kernel.org> On Behalf Of Yu, Fenghua
> Sent: Tuesday, November 13, 2018 3:50 PM
> To: Moger, Babu <Babu.Moger@amd.com>; tglx@linutronix.de;
> mingo@redhat.com; bp@alien8.de; corbet@lwn.net; Chatre, Reinette
> <reinette.chatre@intel.com>; peterz@infradead.org;
> gregkh@linuxfoundation.org; davem@davemloft.net; akpm@linux-
> foundation.org
> Cc: hpa@zytor.com; x86@kernel.org; mchehab+samsung@kernel.org;
> arnd@arndb.de; kstewart@linuxfoundation.org; pombredanne@nexb.com;
> rafael@kernel.org; kirill.shutemov@linux.intel.com; Luck, Tony
> <tony.luck@intel.com>; qianyue.zj@alibaba-inc.com; Shen, Xiaochen
> <xiaochen.shen@intel.com>; pbonzini@redhat.com; Singh, Brijesh
> <brijesh.singh@amd.com>; Hurwitz, Sherry <sherry.hurwitz@amd.com>;
> dwmw2@infradead.org; Lendacky, Thomas <Thomas.Lendacky@amd.com>;
> luto@kernel.org; joro@8bytes.org; jannh@google.com;
> vkuznets@redhat.com; rian@alum.mit.edu; jpoimboe@redhat.com; linux-
> kernel@vger.kernel.org; linux-doc@vger.kernel.org; Yu, Fenghua
> <fenghua.yu@intel.com>
> Subject: RE: [PATCH v7 11/13] arch/x86: Introduce QOS feature for AMD
>
> > From: Moger, Babu [mailto:Babu.Moger@amd.com]
> > Subject: [PATCH v7 11/13] arch/x86: Introduce QOS feature for AMD
> > The specification for this feature is available at
> > https://developer.amd.com/wp-content/resources/56375.pdf
>
> > +bool cbm_validate_amd(char *buf, u32 *data, struct rdt_resource *r) {
> > + if (val > r->default_ctrl) {
> > + rdt_last_cmd_puts("mask out of range\n");
> > + return false;
> > + }
>
> If val is zero, then this closid cannot allocate any cache line.
>
> I'm wondering: does that mean the tasks running with this closid directly
> access memory without cache? Is there any usage for this situation?

I would think any memory access has to happen via cache only. But
I am not sure about the usage of this situation. Will check on that.
Will post if I get any more information. But I can say that it is
allowed to have mask as zero. Looking at the specs
https://developer.amd.com/wp-content/resources/56375.pdf

The bits which are set in the various L3_MASK_n registers do not have to be
contiguous and may overlap in any desired combination. If an L3_MASK_n
register is programmed with all 0's, that COS will be prevented from allocating
any lines in the L3 cache. At reset, all L3_MASK_n registers are initialized to all
1's, allowing all processors to use the entire L3 cache accessible to them.

>
> Thanks.
>
> -Fenghua

\
 
 \ /
  Last update: 2018-11-14 17:39    [W:0.095 / U:0.532 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site