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SubjectRe: [PATCH v5 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller
Date
Hi Yogesh,

On 14.11.18 09:39, Yogesh Narayan Gaur wrote:
> Hi Frieder,
>
> I have tried v5 version of the patch and have observed that Read is failing for CS1.

Thanks a lot for doing the test. I really appreciate it.

> In my target 2 flash devices are connected on same bus i.e. A1 -> CS0 and A2 -> CS1.
>
> On initial debugging, I figured that Read is failing for the AHB mode i.e. if I attempt to read data size less than rxfifo read is working fine without any issue.
>
> For data size more than rxfifo Read out data is content of same requested address of CS0.
> mtd_debug read /dev/mtd1 0xf00000 0x70 read --> Data is correct
> mtd_debug read /dev/mtd1 0xf00000 0x100 read --> Data is in-correct and data content are of the address 0xf00000 of CS0 connected flash device.

Ok, I will have a look at what could make the chip selection fail in
case of AHB read.

> On the setup where you have done testing, did AHB mode read is being verified for CS1?

No, I currently have only hardware with CS0 connected. So I didn't test
with CS1.

>
> I am doing further debugging of this issue.

Thanks,
Frieder
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