lkml.org 
[lkml]   [2018]   [Nov]   [12]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 4.19 283/361] powerpc/64s/hash: Do not use PPC_INVALIDATE_ERAT on CPUs before POWER9
    Date
    4.19-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Nicholas Piggin <npiggin@gmail.com>

    commit bc276ecba132caccb1fda5863a652c15def2b8c6 upstream.

    PPC_INVALIDATE_ERAT is slbia IH=7 which is a new variant introduced
    with POWER9, and the result is undefined on earlier CPUs.

    Commits 7b9f71f974 ("powerpc/64s: POWER9 machine check handler") and
    d4748276ae ("powerpc/64s: Improve local TLB flush for boot and MCE on
    POWER9") caused POWER7/8 code to use this instruction. Remove it. An
    ERAT flush can be made by invalidatig the SLB, but before POWER9 that
    requires a flush and rebolt.

    Fixes: 7b9f71f974 ("powerpc/64s: POWER9 machine check handler")
    Fixes: d4748276ae ("powerpc/64s: Improve local TLB flush for boot and MCE on POWER9")
    Cc: stable@vger.kernel.org # v4.11+
    Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
    Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    arch/powerpc/kernel/mce_power.c | 7 +++++++
    arch/powerpc/mm/hash_native_64.c | 4 ++--
    2 files changed, 9 insertions(+), 2 deletions(-)

    --- a/arch/powerpc/kernel/mce_power.c
    +++ b/arch/powerpc/kernel/mce_power.c
    @@ -89,6 +89,13 @@ static void flush_and_reload_slb(void)

    static void flush_erat(void)
    {
    +#ifdef CONFIG_PPC_BOOK3S_64
    + if (!early_cpu_has_feature(CPU_FTR_ARCH_300)) {
    + flush_and_reload_slb();
    + return;
    + }
    +#endif
    + /* PPC_INVALIDATE_ERAT can only be used on ISA v3 and newer */
    asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
    }

    --- a/arch/powerpc/mm/hash_native_64.c
    +++ b/arch/powerpc/mm/hash_native_64.c
    @@ -115,6 +115,8 @@ static void tlbiel_all_isa300(unsigned i
    tlbiel_hash_set_isa300(0, is, 0, 2, 1);

    asm volatile("ptesync": : :"memory");
    +
    + asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");
    }

    void hash__tlbiel_all(unsigned int action)
    @@ -140,8 +142,6 @@ void hash__tlbiel_all(unsigned int actio
    tlbiel_all_isa206(POWER7_TLB_SETS, is);
    else
    WARN(1, "%s called on pre-POWER7 CPU\n", __func__);
    -
    - asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");
    }

    static inline unsigned long ___tlbie(unsigned long vpn, int psize,

    \
     
     \ /
      Last update: 2018-11-12 00:51    [W:4.129 / U:0.408 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site