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    Subject[PATCH 3.16 220/366] x86/bugs: Add AMD's variant of SSB_NO
    3.16.61-rc1 review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>

    commit 24809860012e0130fbafe536709e08a22b3e959e upstream.

    The AMD document outlining the SSBD handling
    124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf
    mentions that the CPUID 8000_0008.EBX[26] will mean that the
    speculative store bypass disable is no longer needed.

    A copy of this document is available at:
    https://bugzilla.kernel.org/show_bug.cgi?id=199889

    Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Cc: Tom Lendacky <thomas.lendacky@amd.com>
    Cc: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>
    Cc: kvm@vger.kernel.org
    Cc: andrew.cooper3@citrix.com
    Cc: Andy Lutomirski <luto@kernel.org>
    Cc: "H. Peter Anvin" <hpa@zytor.com>
    Cc: Borislav Petkov <bp@suse.de>
    Cc: David Woodhouse <dwmw@amazon.co.uk>
    Link: https://lkml.kernel.org/r/20180601145921.9500-2-konrad.wilk@oracle.com
    [bwh: Backported to 3.16:
    - The feature bit is in feature word 11
    - Adjust filename, context]
    Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
    ---
    arch/x86/include/asm/cpufeature.h | 1 +
    arch/x86/kernel/cpu/common.c | 3 ++-
    arch/x86/kvm/cpuid.c | 2 +-
    3 files changed, 4 insertions(+), 2 deletions(-)

    --- a/arch/x86/include/asm/cpufeature.h
    +++ b/arch/x86/include/asm/cpufeature.h
    @@ -257,6 +257,7 @@
    #define X86_FEATURE_AMD_IBRS (11*32+14) /* "" Indirect Branch Restricted Speculation */
    #define X86_FEATURE_AMD_STIBP (11*32+15) /* "" Single Thread Indirect Branch Predictors */
    #define X86_FEATURE_VIRT_SSBD (11*32+25) /* Virtualized Speculative Store Bypass Disable */
    +#define X86_FEATURE_AMD_SSB_NO (11*32+26) /* "" Speculative Store Bypass is fixed in hardware. */

    /*
    * BUG word(s)
    --- a/arch/x86/kernel/cpu/common.c
    +++ b/arch/x86/kernel/cpu/common.c
    @@ -865,7 +865,8 @@ static void __init cpu_set_bug_bits(stru
    rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);

    if (!x86_match_cpu(cpu_no_spec_store_bypass) &&
    - !(ia32_cap & ARCH_CAP_SSB_NO))
    + !(ia32_cap & ARCH_CAP_SSB_NO) &&
    + !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
    setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);

    if (x86_match_cpu(cpu_no_speculation))
    --- a/arch/x86/kvm/cpuid.c
    +++ b/arch/x86/kvm/cpuid.c
    @@ -302,7 +302,7 @@ static inline int __do_cpuid_ent(struct

    /* cpuid 0x80000008.ebx */
    const u32 kvm_cpuid_8000_0008_ebx_x86_features =
    - F(AMD_IBPB) | F(AMD_IBRS) | F(VIRT_SSBD);
    + F(AMD_IBPB) | F(AMD_IBRS) | F(VIRT_SSBD) | F(AMD_SSB_NO);

    /* cpuid 0xC0000001.edx */
    const u32 kvm_supported_word5_x86_features =
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