Messages in this thread | | | Subject | Re: [PATCH] arm_pmu: Delete incorrect cache event mapping for some armv8_pmuv3 events. | From | John Garry <> | Date | Fri, 5 Oct 2018 13:27:08 +0100 |
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On 04/10/2018 13:22, Will Deacon wrote: > Hi Ganapat, > > On Thu, Oct 04, 2018 at 11:12:09AM +0530, Ganapatrao Kulkarni wrote: >> can you please pull this patch? > > I still don't like the idea of just removing events like this, especially > when other architectures (including some x86 and Power CPUs afaict) playa > similar games for generic events, and these events do actually appear in > user code. > > I also don't understand why you remove the TLB events. I think that logic > would imply we should remove all of the events, because we can't distinguish > prefetches from reads either. If we want to be consistent, then I think > we should just remove the OP_WRITE events for L1D and BPU -- would you be > ok with that instead? > > Also, looking at the code, I think our PMCEID parsing is broken for 8.1 > parts, where the upper 32 bits of the register are offset by 0x4000 in the > event numbering space. >
Here's something I noticed: static ssize_t armv8pmu_events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page) { struct perf_pmu_events_attr *pmu_attr;
pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
return sprintf(page, "event=0x%03llx\n", pmu_attr->id);
Should this be min width now be 4, since event width is now 16 bits (even though I don't know why we need to specify this width at all)?
Cheers, John
> Will > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > . >
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