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SubjectRe: [RFR] Store tearing
On Mon, Oct 29, 2018 at 12:10:03AM +0100, Andrea Parri wrote:
> Hopefully, with Paul's proper email address this time,
>
> Andrea
>
> On Mon, Oct 29, 2018 at 12:06:27AM +0100, Andrea Parri wrote:
> > Hi,
> >
> > memory-barriers.txt says:
> >
> > [on "store tearing"]
> >
> > "In fact, a recent bug (since fixed) caused GCC to incorrectly use
> > this optimization in a volatile store.".
> >
> > I was wondering if you could help me retrieve some reference/discussions
> > about this?

This was quite some time ago, but it involved a 32-bit volatile store
of a constant such as 0x10001. The machine in question had a narrow
store-immediate instruction, so the compiler emitted a pair of 16-bit
store-immediate instructions. This bug was fixed, though only after
significant screaming and shouting.

Thanx, Paul

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