[lkml]   [2018]   [Oct]   [24]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: [PATCH v2 12/15] clk: sunxi-ng: a64: Add min and max rate for PLL_MIPI
On Tue, Oct 23, 2018 at 09:20:32PM +0530, Jagan Teki wrote:
> A64 manual say PLL_MIPI rates are 500MHz to 1.4GHz, but
> using minimum 500MHz can't release the clock and which
> is not working.
> So use working minimum rate as 300MHz which is tested on
> Bananapi DSI panel.

I'm not quite sure what you mean by that. What do you mean by "500MHz
can't release the clock"? Why would 300MHz work better then? Should be
avoid reaching 500MHz if it's a frequency in the valid range?


Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
[unhandled content-type:application/pgp-signature]
 \ /
  Last update: 2018-10-24 20:14    [W:0.169 / U:25.192 seconds]
©2003-2018 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site