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SubjectRe: [PATCH] ARM: debug: enable UART1 for socfpga Cyclone5

On 10/23/2018 09:44 AM, Clément Péron wrote:
> HI Dinh,
> On Tue, 23 Oct 2018 at 16:04, Dinh Nguyen <> wrote:
>> Hi Clément,
>> On 10/09/2018 06:28 AM, Clément Péron wrote:
>>> Cyclone5 and Arria10 doesn't have the same memory map for UART1.
>>> Split the SOCFPGA_UART1 into 2 options to allow debugging on UART1 for Cylone5.
>> I'm not sure the need for this patch. Are there any cyclone5 based
>> boards that has UART1 as the debug uart? I see that all of them are
>> using UART0.
> There is no upstream device with this UART used. But the board I have
> use it, and there is no limitation to not have it available upstream
> no ?

I see. Then I don't think the patch is applicable because none of the
upstream devices need it. Now, if you were to upstream your board that
uses UART1, then there will be a case for this patch. Do you agree?


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