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    Subject[PATCH v5 04/13] arch/x86: Bring all the macros to resctrl.h
    Date
    Bring all the macros to resctrl.h and rename for consistency.

    Signed-off-by: Babu Moger <babu.moger@amd.com>
    ---
    arch/x86/kernel/cpu/resctrl.c | 3 ---
    arch/x86/kernel/cpu/resctrl.h | 5 +++++
    arch/x86/kernel/cpu/resctrl_monitor.c | 7 ++-----
    3 files changed, 7 insertions(+), 8 deletions(-)

    diff --git a/arch/x86/kernel/cpu/resctrl.c b/arch/x86/kernel/cpu/resctrl.c
    index 6c1199f7f28e..befc4eee0f07 100644
    --- a/arch/x86/kernel/cpu/resctrl.c
    +++ b/arch/x86/kernel/cpu/resctrl.c
    @@ -33,9 +33,6 @@
    #include <asm/resctrl_sched.h>
    #include "resctrl.h"

    -#define MBA_IS_LINEAR 0x4
    -#define MBA_MAX_MBPS U32_MAX
    -
    /* Mutex to protect rdtgroup access. */
    DEFINE_MUTEX(rdtgroup_mutex);

    diff --git a/arch/x86/kernel/cpu/resctrl.h b/arch/x86/kernel/cpu/resctrl.h
    index abf5c7e4c625..e5f7bf6a8d09 100644
    --- a/arch/x86/kernel/cpu/resctrl.h
    +++ b/arch/x86/kernel/cpu/resctrl.h
    @@ -12,6 +12,9 @@
    #define IA32_L2_CBM_BASE 0xd10
    #define IA32_MBA_THRTL_BASE 0xd50

    +#define IA32_QM_CTR 0x0c8e
    +#define IA32_QM_EVTSEL 0x0c8d
    +
    #define L3_QOS_CDP_ENABLE 0x01ULL

    #define L2_QOS_CDP_ENABLE 0x01ULL
    @@ -29,6 +32,8 @@
    #define MBM_CNTR_WIDTH 24
    #define MBM_OVERFLOW_INTERVAL 1000
    #define MAX_MBA_BW 100u
    +#define MBA_IS_LINEAR 0x4
    +#define MBA_MAX_MBPS U32_MAX

    #define RMID_VAL_ERROR BIT_ULL(63)
    #define RMID_VAL_UNAVAIL BIT_ULL(62)
    diff --git a/arch/x86/kernel/cpu/resctrl_monitor.c b/arch/x86/kernel/cpu/resctrl_monitor.c
    index 68dbdbbf47df..ad0107bc16a0 100644
    --- a/arch/x86/kernel/cpu/resctrl_monitor.c
    +++ b/arch/x86/kernel/cpu/resctrl_monitor.c
    @@ -28,9 +28,6 @@
    #include <asm/cpu_device_id.h>
    #include "resctrl.h"

    -#define MSR_IA32_QM_CTR 0x0c8e
    -#define MSR_IA32_QM_EVTSEL 0x0c8d
    -
    struct rmid_entry {
    u32 rmid;
    int busy;
    @@ -97,8 +94,8 @@ static u64 __rmid_read(u32 rmid, u32 eventid)
    * IA32_QM_CTR.Error (bit 63) and IA32_QM_CTR.Unavailable (bit 62)
    * are error bits.
    */
    - wrmsr(MSR_IA32_QM_EVTSEL, eventid, rmid);
    - rdmsrl(MSR_IA32_QM_CTR, val);
    + wrmsr(IA32_QM_EVTSEL, eventid, rmid);
    + rdmsrl(IA32_QM_CTR, val);

    return val;
    }
    --
    2.17.1
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