lkml.org 
[lkml]   [2018]   [Oct]   [11]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    Date
    From
    SubjectRe: [PATCH v5 01/27] x86/cpufeatures: Add CPUIDs for Control Flow Enforcement Technology (CET)
    On Thu, Oct 11, 2018 at 08:14:57AM -0700, Yu-cheng Yu wrote:
    > Add CPUIDs for Control Flow Enforcement Technology (CET).

    This is not "CPUIDs" but feature flags. Fix the subject too pls.

    > CPUID.(EAX=7,ECX=0):ECX[bit 7] Shadow stack
    > CPUID.(EAX=7,ECX=0):EDX[bit 20] Indirect branch tracking
    >
    > Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
    > ---
    > arch/x86/include/asm/cpufeatures.h | 2 ++
    > 1 file changed, 2 insertions(+)
    >
    > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
    > index 89a048c2faec..142b15da06fd 100644
    > --- a/arch/x86/include/asm/cpufeatures.h
    > +++ b/arch/x86/include/asm/cpufeatures.h
    > @@ -321,6 +321,7 @@
    > #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */
    > #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */
    > #define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
    > +#define X86_FEATURE_SHSTK (16*32+ 7) /* Shadow Stack */
    > #define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */
    > #define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */
    > #define X86_FEATURE_VPCLMULQDQ (16*32+10) /* Carry-Less Multiplication Double Quadword */
    > @@ -341,6 +342,7 @@
    > #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */
    > #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
    > #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
    > +#define X86_FEATURE_IBT (18*32+20) /* Indirect Branch Tracking */
    > #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
    > #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
    > #define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */
    > --

    With that addressed:

    Reviewed-by: Borislav Petkov <bp@suse.de>

    --
    Regards/Gruss,
    Boris.

    Good mailing practices for 400: avoid top-posting and trim the reply.

    \
     
     \ /
      Last update: 2018-10-11 18:45    [W:4.096 / U:0.124 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site