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    Subject[PATCH v6 02/15] clk: ingenic: Fix recalc_rate for clocks with fixed divider
    Date
    Previously, the clocks with a fixed divider would report their rate
    as being the same as the one of their parent, independently of the
    divider in use. This commit fixes this behaviour.

    This went unnoticed as neither the jz4740 nor the jz4780 CGU code
    have clocks with fixed dividers yet.

    Signed-off-by: Paul Cercueil <paul@crapouillou.net>
    Acked-by: Stephen Boyd <sboyd@codeaurora.org>
    ---
    drivers/clk/ingenic/cgu.c | 2 ++
    1 file changed, 2 insertions(+)

    v2: No changes
    v3: No changes
    v4: No changes
    v5: No changes
    v6: No changes

    diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
    index ab393637f7b0..a2e73a6d60fd 100644
    --- a/drivers/clk/ingenic/cgu.c
    +++ b/drivers/clk/ingenic/cgu.c
    @@ -328,6 +328,8 @@ ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
    div *= clk_info->div.div;

    rate /= div;
    + } else if (clk_info->type & CGU_CLK_FIXDIV) {
    + rate /= clk_info->fixdiv.div;
    }

    return rate;
    --
    2.11.0
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