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SubjectRe: [PATCH 0/7] IBRS patch series
On Thu, 2018-01-04 at 19:40 +0000, Andrew Cooper wrote:
> Also remember that sibling threads share a BTB, so you can't rely on
> isolated straight-line codepath on the current cpu for safety. (e.g. by
> issuing an IBPB on every entry to supervisor mode).

That is just one of a whole litany of reasons the RSB gets flushed,
*many* of which were individually sufficient for us to throw our toys
out of the pram and say "OK, this doesn't work on Skylake".
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