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SubjectRe: [PATCH v2 3/8] x86/msr: Add definitions for new speculation control MSRs
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On 01/21/2018, 10:49 AM, David Woodhouse wrote:
> Add MSR and bit definitions for SPEC_CTRL, PRED_CMD and ARCH_CAPABILITIES.
>
> See Intel's 336996-Speculative-Execution-Side-Channel-Mitigations.pdf
>
> Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
> ---
> arch/x86/include/asm/msr-index.h | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index fa11fb1..3e50463 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -42,6 +42,13 @@
> #define MSR_PPIN_CTL 0x0000004e
> #define MSR_PPIN 0x0000004f
>
> +#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */
> +#define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */
> +#define SPEC_CTRL_STIBP (1 << 1) /* Single Thread Indirect Branch Predictors */
> +
> +#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
> +#define PRED_CMD_IBPB (1 << 0) /* Indirect Branch Prediction Barrier */
> +
> #define MSR_IA32_PERFCTR0 0x000000c1
> #define MSR_IA32_PERFCTR1 0x000000c2
> #define MSR_FSB_FREQ 0x000000cd
> @@ -60,6 +67,10 @@
> #define MSR_IA32_BBL_CR_CTL 0x00000119
> #define MSR_IA32_BBL_CR_CTL3 0x0000011e
>
> +#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
> +#define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */
> +#define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */

Is there any reason why all 3 are not properly sorted?
0x04e > 0x048
0x119 > 0x10a

> #define MSR_IA32_SYSENTER_CS 0x00000174
> #define MSR_IA32_SYSENTER_ESP 0x00000175
> #define MSR_IA32_SYSENTER_EIP 0x00000176
>

thanks,
--
js
suse labs

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