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SubjectRe: 4.15-rc6 PTI regression: L1 TLB mismatch MCE on Athlon64
On Tue, Jan 02, 2018 at 10:49:16PM +0200, Meelis Roos wrote:
> This is on a socket 939 Athlon64 3500+, with PTI enabled.


> [ 316.384669] mce: [Hardware Error]: Machine check events logged
> [ 316.384698] [Hardware Error]: Corrected error, no action required.
> [ 316.384719] [Hardware Error]: CPU:0 (f:2f:2) MC1_STATUS[-|CE|-|-|AddrV]: 0x9400000000010011
> [ 316.384742] [Hardware Error]: Error Addr: 0x0000ffff81e000e0

That's the [47:12] slice of the virtual address which it tried to execute.

According to our map in mm.txt:

ffff800000000000 - ffff87ffffffffff (=43 bits) guard hole, reserved for hypervisor



which makes me think: WTF now?!

I don't see any hypervisor happening in dmesg...

> [ 316.384757] [Hardware Error]: MC1 Error: L1 TLB multimatch.
> [ 316.384774] [Hardware Error]: cache level: L1, tx: INSN
> These MCE-s do not happen on 4.14 and 4.15.0-rc4-00041-gace52288edf0.
> They do happen on each boot into 4.15-rc6. Will try to bisect.

Please do. And try -rc5 too.

And then Linus' pti merges:


> I understand there exist patches that turn off PTI on AMD CPUs but the
> MCE-s seem still interesting.

Yes, there is:

> Same kernel with "nopti" boot command line option does not show the
> MCE-s either.
> When the MCE-s happen, they happen with 5 minute interval or slightly
> more, like this (excerpt from grep mce: /var/log/kern.log, not full
> dmesg). The first ones always happen at 316 and 627 seconds after
> bootup.

That's the 5 minute default check interval for corrected errors. You can do

# echo 10 > /sys/devices/system/machinecheck/machinecheck0/check_interval

to decrease it.


Good mailing practices for 400: avoid top-posting and trim the reply.

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