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SubjectRe: [PATCH] drm/arm/malidp: Disable pixel alpha blending for colors that do not have alpha
Hi Ayan,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm/drm-next]
[also build test ERROR on v4.15-rc8 next-20180112]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url: https://github.com/0day-ci/linux/commits/Ayan-Halder/drm-arm-malidp-Disable-pixel-alpha-blending-for-colors-that-do-not-have-alpha/20180115-080603
base: git://people.freedesktop.org/~airlied/linux.git drm-next
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm

All errors (new ones prefixed by >>):

drivers/gpu/drm/arm/malidp_planes.c: In function 'malidp_de_plane_update':
>> drivers/gpu/drm/arm/malidp_planes.c:275:42: error: 'const struct drm_format_info' has no member named 'alpha'
u8 alpha_bits = plane->state->fb->format->alpha;
^~

vim +275 drivers/gpu/drm/arm/malidp_planes.c

267
268 static void malidp_de_plane_update(struct drm_plane *plane,
269 struct drm_plane_state *old_state)
270 {
271 struct malidp_plane *mp;
272 struct malidp_plane_state *ms = to_malidp_plane_state(plane->state);
273 u32 src_w, src_h, dest_w, dest_h, val;
274 int i;
> 275 u8 alpha_bits = plane->state->fb->format->alpha;
276
277 mp = to_malidp_plane(plane);
278
279 /* convert src values from Q16 fixed point to integer */
280 src_w = plane->state->src_w >> 16;
281 src_h = plane->state->src_h >> 16;
282 dest_w = plane->state->crtc_w;
283 dest_h = plane->state->crtc_h;
284
285 malidp_hw_write(mp->hwdev, ms->format, mp->layer->base);
286
287 for (i = 0; i < ms->n_planes; i++) {
288 /* calculate the offset for the layer's plane registers */
289 u16 ptr = mp->layer->ptr + (i << 4);
290 dma_addr_t fb_addr = drm_fb_cma_get_gem_addr(plane->state->fb,
291 plane->state, i);
292
293 malidp_hw_write(mp->hwdev, lower_32_bits(fb_addr), ptr);
294 malidp_hw_write(mp->hwdev, upper_32_bits(fb_addr), ptr + 4);
295 }
296 malidp_de_set_plane_pitches(mp, ms->n_planes,
297 plane->state->fb->pitches);
298
299 malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
300 mp->layer->base + MALIDP_LAYER_SIZE);
301
302 malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h),
303 mp->layer->base + MALIDP_LAYER_COMP_SIZE);
304
305 malidp_hw_write(mp->hwdev, LAYER_H_VAL(plane->state->crtc_x) |
306 LAYER_V_VAL(plane->state->crtc_y),
307 mp->layer->base + MALIDP_LAYER_OFFSET);
308
309 if (mp->layer->id == DE_SMART)
310 malidp_hw_write(mp->hwdev,
311 LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
312 mp->layer->base + MALIDP550_LS_R1_IN_SIZE);
313
314 /* first clear the rotation bits */
315 val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL);
316 val &= ~LAYER_ROT_MASK;
317
318 /* setup the rotation and axis flip bits */
319 if (plane->state->rotation & DRM_MODE_ROTATE_MASK)
320 val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) <<
321 LAYER_ROT_OFFSET;
322 if (plane->state->rotation & DRM_MODE_REFLECT_X)
323 val |= LAYER_H_FLIP;
324 if (plane->state->rotation & DRM_MODE_REFLECT_Y)
325 val |= LAYER_V_FLIP;
326
327 val &= ~LAYER_COMP_MASK;
328 if (alpha_bits > 0) {
329
330 /*
331 * always enable pixel alpha blending until we have a way to change
332 * blend modes
333 */
334 val |= LAYER_COMP_PIXEL;
335 } else {
336
337 /*
338 * do not enable pixel alpha blending as the color channel does not
339 * have any alpha information
340 */
341 val |= LAYER_COMP_PLANE;
342
343 /* Set layer alpha coefficient to 0xff ie fully opaque */
344 val |= LAYER_ALPHA(0xff);
345 }
346
347 val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK);
348 if (plane->state->crtc) {
349 struct malidp_crtc_state *m =
350 to_malidp_crtc_state(plane->state->crtc->state);
351
352 if (m->scaler_config.scale_enable &&
353 m->scaler_config.plane_src_id == mp->layer->id)
354 val |= LAYER_FLOWCFG(LAYER_FLOWCFG_SCALE_SE);
355 }
356
357 /* set the 'enable layer' bit */
358 val |= LAYER_ENABLE;
359
360 malidp_hw_write(mp->hwdev, val,
361 mp->layer->base + MALIDP_LAYER_CONTROL);
362 }
363

---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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