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SubjectRe: [PATCH 30/40] drm/rockchip: Flush PSR before committing modeset disables/enables
Hi Thierry,

On Tue, Jan 16, 2018 at 2:16 AM, Thierry Escande
<thierry.escande@collabora.com> wrote:
> From: Tomasz Figa <tfiga@chromium.org>
>
> Currently PSR flush is triggered from CRTC's .atomic_begin() callback,
> which is executed after modeset disables and enables and before plane
> updates are committed. Since PSR flush and re-enable can be triggered
> asynchronously by external sources (input event, delayed work), it can
> race with hardware programming done in the aforementioned stages.
>
> To avoid the race, we can trigger PSR flush before committing modeset
> disables/enables. This also has the advantage of removing some
> PSR-specific knowledge from the VOP driver.

FYI, this patch was eventually found to still leave few unsolved races
and was later replaced with a more comprehensive redesign of Rockchip
PSR code. Please refer to the following Chromium patches:

https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/430429/
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/436571/
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/438228/
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/438229/
<- This one effectively replaces all the code added in this patch.
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/438230/

Best regards,
Tomasz

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