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    Subject[PATCH 3/4] x86/kernel: Drastically reduce the number of firmware bug warnings
    Prior to the TSC ADJUST MSR being available, the method to set TSC's in
    sync with each other naturally caused a small skew between cpu threads.
    This was NOT a firmware bug at the time so introducing a whole avalanche
    of alarming warning messages might cause unnecessary concern and customer
    complaints. (Example: >3000 msgs in a 32 socket Skylake system.)

    Simply report the warning condition, if possible do the necessary fixes,
    and move on.

    Signed-off-by: Mike Travis <mike.travis@hpe.com>
    Reviewed-by: Dimitri Sivanich <dimitri.sivanich@hpe.com>
    Reviewed-by: Russ Anderson <russ.anderson@hpe.com>
    ---
    arch/x86/kernel/tsc_sync.c | 9 +++------
    1 file changed, 3 insertions(+), 6 deletions(-)

    --- linux.orig/arch/x86/kernel/tsc_sync.c
    +++ linux/arch/x86/kernel/tsc_sync.c
    @@ -123,10 +123,9 @@ bool tsc_store_and_check_tsc_adjust(bool
    * Compare the boot value and complain if it differs in the
    * package.
    */
    - if (bootval != ref->bootval) {
    - pr_warn(FW_BUG "TSC ADJUST differs: Reference CPU%u: %lld CPU%u: %lld\n",
    - refcpu, ref->bootval, cpu, bootval);
    - }
    + if (bootval != ref->bootval)
    + printk_once(FW_BUG "TSC ADJUST differs within socket(s), fixing all errors\n");
    +
    /*
    * The TSC_ADJUST values in a package must be the same. If the boot
    * value on this newly upcoming CPU differs from the adjustment
    @@ -134,8 +133,6 @@ bool tsc_store_and_check_tsc_adjust(bool
    * adjusted value.
    */
    if (bootval != ref->adjusted) {
    - pr_warn("TSC ADJUST synchronize: Reference CPU%u: %lld CPU%u: %lld\n",
    - refcpu, ref->adjusted, cpu, bootval);
    cur->adjusted = ref->adjusted;
    wrmsrl(MSR_IA32_TSC_ADJUST, ref->adjusted);
    }
    --

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