Messages in this thread | | | Date | Wed, 13 Sep 2017 10:01:46 -0700 (PDT) | Subject | Re: [patches] Re: [PATCH v8 11/18] RISC-V: Atomic and Locking Code | From | Palmer Dabbelt <> |
| |
On Wed, 13 Sep 2017 08:28:30 PDT (-0700), Arnd Bergmann wrote: > On Tue, Sep 12, 2017 at 11:57 PM, Palmer Dabbelt <palmer@dabbelt.com> wrote: >> This contains all the code that directly interfaces with the RISC-V >> memory model. While this code corforms to the current RISC-V ISA >> specifications (user 2.2 and priv 1.10), the memory model is somewhat >> underspecified in those documents. There is a working group that hopes >> to produce a formal memory model by the end of the year, but my >> understanding is that the basic definitions we're relying on here won't >> change significantly. >> >> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> > > I've read through the current definition of the I/O accessors again, as we > discussed those before, and this version looks good to me. I've also > looked briefly at the other helpers in this patch and found nothing > surprising in there, so feel free to add > > Reviewed-by: Arnd Bergmann <arnd@arndb.de> > > to the patch.
Thanks for all your time!
| |