Messages in this thread | | | Date | Thu, 3 Aug 2017 17:48:34 +0200 | From | Boris Brezillon <> | Subject | Re: [PATCH v2 02/25] mtd: nand: qcom: program NAND_DEV_CMD_VLD register |
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On Wed, 19 Jul 2017 17:17:50 +0530 Abhishek Sahu <absahu@codeaurora.org> wrote:
> The current driver is failing without complete bootchain since > NAND_DEV_CMD_VLD value is not valid. > > Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
BTW, do you want to backport this fix? Maybe you add Fixes and Cc-stable tags...
> --- > drivers/mtd/nand/qcom_nandc.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c > index bc0408c..f3b995d 100644 > --- a/drivers/mtd/nand/qcom_nandc.c > +++ b/drivers/mtd/nand/qcom_nandc.c > @@ -148,6 +148,9 @@ > #define FETCH_ID 0xb > #define RESET_DEVICE 0xd > > +/* Value for NAND_DEV_CMD_VLD */ > +#define NAND_DEV_CMD_VLD_VAL 0x1d > + > /* > * the NAND controller performs reads/writes with ECC in 516 byte chunks. > * the driver calls the chunks 'step' or 'codeword' interchangeably > @@ -1972,6 +1975,7 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc) > { > /* kill onenand */ > nandc_write(nandc, SFLASHC_BURST_CFG, 0); > + nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL); > > /* enable ADM DMA */ > nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
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