Messages in this thread | | | Subject | Re: [RFC][PATCH 1/5] mm: Rework {set,clear,mm}_tlb_flush_pending() | From | Benjamin Herrenschmidt <> | Date | Wed, 02 Aug 2017 23:57:04 +1000 |
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On Wed, 2017-08-02 at 10:11 +0200, Peter Zijlstra wrote:
> which should be completely ordered against anything prior and anything > following, and is I think the behaviour we want from TLB flushes in > general, but is very much not provided by a number of architectures > afaict. > > Ah, found the hash-64 code, yes that's good too. The hash32 code lives > in asm and confuses me, it has a bunch of SYNC, SYNC_601 and isync in. > The nohash variant seems to do a isync after tlbwe, but again no clue.
Doing some archeology ? :-)
In the hash32 days ptesync didn't exist, sync had all the needed semantics. tlbew isn't a proper invalidate per-se, but isync will flush the shadow TLBs, but I wouldn't bother too much about these, if needed I can go fix them.
> Now, do I go and attempt fixing all that needs fixing? > > > x86 is good, our CR3 writes or INVLPG stuff is fully serializing. > > arm is good, it does DSB ISH before and after > > arm64 looks good too, although it plays silly games with the first > barrier, but I trust that to be sufficient. > > But I'll have to go dig up arch manuals for the rest, if they include > the relevant information at all of course :/
Ben.
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