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SubjectRe: [RFC 02/12] clk: qcom: flag for 64 bit CONFIG_CTL
On 2017-07-29 00:03, Stephen Boyd wrote:
> On 07/27, Abhishek Sahu wrote:
>> diff --git a/drivers/clk/qcom/clk-alpha-pll.c
>> b/drivers/clk/qcom/clk-alpha-pll.c
>> index 47a1da3..e6cde2d 100644
>> --- a/drivers/clk/qcom/clk-alpha-pll.c
>> +++ b/drivers/clk/qcom/clk-alpha-pll.c
>> @@ -118,7 +118,10 @@ void clk_alpha_pll_configure(struct clk_alpha_pll
>> *pll, struct regmap *regmap,
>> regmap_write(regmap, off + PLL_L_VAL, config->l);
>> regmap_write(regmap, off + PLL_ALPHA_VAL, config->alpha);
>> regmap_write(regmap, off + PLL_CONFIG_CTL, config->config_ctl_val);
>> - regmap_write(regmap, off + PLL_CONFIG_CTL_U,
>> config->config_ctl_hi_val);
>> +
>> + if (pll->flags & SUPPORTS_64BIT_CONFIG_CTL)
>> + regmap_write(regmap, off + PLL_CONFIG_CTL_U,
>> + config->config_ctl_hi_val);
>
> Is there a hole there? I mean a RAZ/WI register so we can just
> keep writing it and not care?

We don't have hole for most of the alpha PLL. The offset for
CONFIG_CTL itself is not same for all types of Alpha PLL
and the same is being handled in patch 4 of this patch
series.

Spark PLL
CONFIG_CTL 0x18
TEST_CTL 0x1C
TEST_CTL_U 0x20

Brammo PLL
CONFIG_CTL 0x18
TEST_CTL 0x1C
PLL_STATUS 0x24

Hyuara PLL
CONFIG_CTL 0x14
CONFIG_CTL_U 0x18
TEST_CTL 0x1c

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