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Subject[PATCH v2 0/4] clk: meson: gxbb-aoclk: Add CEC 32k clock
In order to support the standalone CEC Controller on the Amlogic SoCs,
a specific CEC 32K clock must be handled in the AO domain.

The CEC 32K AO Clock is a dual divider with dual counter to provide a more
precise 32768Hz clock for the CEC subsystem from the external xtal.

The AO clocks management registers are spread among the AO register space,
so this patch also adds management of these registers mappings then uses them
for the CEC 32K AO clock management.

This patchset :
- updates the bindings accordingly
- switch driver to new bindings
- adds the CEC 32k clock
- adds the clock binding entry

The DT Update will be sent in another patchset.

Changes since v1 at [1] :
- move bindings to parent syscon node and move clkc to subnode
- switch aoclkc to use regmap only register access
- introduce aoclk-regmap-gate for this purpose until regmap clocks are generic


Neil Armstrong (4):
dt-bindings: clock: amlogic,gxbb-aoclkc: Update bindings
clk: meson: gxbb-aoclk: Switch to regmap for register access
dt-bindings: clock: gxbb-aoclk: Add CEC 32k clock
clk: meson: gxbb-aoclk: Add CEC 32k clock

.../bindings/clock/amlogic,gxbb-aoclkc.txt | 22 ++-
drivers/clk/meson/Makefile | 2 +-
drivers/clk/meson/gxbb-aoclk-32k.c | 180 +++++++++++++++++++++
drivers/clk/meson/gxbb-aoclk-regmap.c | 46 ++++++
drivers/clk/meson/gxbb-aoclk.c | 65 +++++---
drivers/clk/meson/gxbb-aoclk.h | 42 +++++
include/dt-bindings/clock/gxbb-aoclkc.h | 1 +
7 files changed, 328 insertions(+), 30 deletions(-)
create mode 100644 drivers/clk/meson/gxbb-aoclk-32k.c
create mode 100644 drivers/clk/meson/gxbb-aoclk-regmap.c
create mode 100644 drivers/clk/meson/gxbb-aoclk.h


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