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SubjectRe: [PATCH v7 2/3] PCI: Enable PCIe Relaxed Ordering if supported
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On 2017/7/27 3:05, Casey Leedom wrote:
> | From: Alexander Duyck <alexander.duyck@gmail.com>
> | Sent: Wednesday, July 26, 2017 11:44 AM
> |
> | On Jul 26, 2017 11:26 AM, "Casey Leedom" <leedom@chelsio.com> wrote:
> | |
> | | I think that the patch will need to be extended to modify
> | | drivers/pci.c/iov.c:sriov_enable() to explicitly turn off
> | | Relaxed Ordering Enable if the Root Complex is marked
> | for no RO TLPs.
> |
> | I'm not sure that would be an issue. Wouldn't most VFs inherit the PF's settings?
>
> Ah yes, you're right. This is covered in section 3.5.4 of the Single Root I/O
> Virtualization and Sharing Specification, Revision 1.0 (September 11, 2007),
> governing the PCIe Capability Device Control register. It states that the VF
> version of that register shall follow the setting of the corresponding PF.
>
> So we should enhance the cxgb4vf/sge.c:t4vf_sge_alloc_rxq() in the same
> way we did for the cxgb4 driver, but that's not critical since the Relaxed
> Ordering Enable supersedes the internal chip's desire to use the Relaxed
> Ordering Attribute.
>
> Ding, send me a note if you'd like me to work that up for you.
>

Ok, you could send the change log and I could put it in the v8 version together,
will you base on the patch 3/3 or build a independence patch?

Ding

> | Also I thought most of the VF configuration space is read only.
>
> Yes, but not all of it. And when a VF is exported to a Virtual Machine,
> then the Hypervisor captures and interprets all accesses to the VF's
> PCIe Configuration Space from the VM.
>
> Thanks again for reminding me of the subtle aspect of the SR_IOV
> specification that I forgot.
>
> Casey
> .
>

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