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    Subject[PATCH 4.9 089/125] MIPS: Actually decode JALX in `__compute_return_epc_for_insn
    Date
    4.9-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Maciej W. Rozycki <macro@imgtec.com>

    commit a9db101b735a9d49295326ae41f610f6da62b08c upstream.

    Complement commit fb6883e5809c ("MIPS: microMIPS: Support handling of
    delay slots.") and actually decode the regular MIPS JALX major
    instruction opcode, the handling of which has been added with the said
    commit for EPC calculation in `__compute_return_epc_for_insn'.

    Fixes: fb6883e5809c ("MIPS: microMIPS: Support handling of delay slots.")
    Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
    Cc: James Hogan <james.hogan@imgtec.com>
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/16394/
    Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    arch/mips/kernel/branch.c | 1 +
    1 file changed, 1 insertion(+)

    --- a/arch/mips/kernel/branch.c
    +++ b/arch/mips/kernel/branch.c
    @@ -556,6 +556,7 @@ int __compute_return_epc_for_insn(struct
    /*
    * These are unconditional and in j_format.
    */
    + case jalx_op:
    case jal_op:
    regs->regs[31] = regs->cp0_epc + 8;
    case j_op:

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