Messages in this thread | | | Date | Wed, 12 Jul 2017 20:44:06 +0800 | From | Boqun Feng <> | Subject | Re: [PATCH 10/17] RISC-V: Atomic and Locking Code |
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On Wed, Jul 12, 2017 at 08:40:49PM +0800, Boqun Feng wrote: [...] > > +/** > > + * set_bit - Atomically set a bit in memory > > + * @nr: the bit to set > > + * @addr: the address to start counting from > > + * > > + * This function is atomic and may not be reordered. See __set_bit() > > This is incorrect, {set,change,clear}_bit() can be reordered, see > Documentation/memory-barriers.txt, they are just relaxed atomics. But I > think you just copy this from x86 code, so maybe x86 code needs help > too, at least claim that's only x86-specific guarantee. > > > + * if you do not require the atomic guarantees. > > + * > > + * Note: there are no guarantees that this function will not be reordered > > + * on non x86 architectures, so if you are writing portable code, > > + * make sure not to rely on its reordering guarantees. > > + *
Hmmm.. the claim is right here ;-/
As your implementation is relax semantics, you'd better rewrite the comment ;-)
Regards, Boqun [unhandled content-type:application/pgp-signature] | |