Messages in this thread Patch in this message | | | From | Ganapatrao Kulkarni <> | Subject | [PATCH v3 1/2] perf: uncore: Adding documentation for ThunderX2 pmu uncore driver | Date | Mon, 5 Jun 2017 12:21:03 +0530 |
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Documentation for the UNCORE PMUs on Cavium's ThunderX2 SoC. The SoC has PMU support in its L3 cache controller (L3C) and in the DDR4 Memory Controller (DMC).
Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> --- Documentation/perf/thunderx2-pmu.txt | 60 ++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/perf/thunderx2-pmu.txt
diff --git a/Documentation/perf/thunderx2-pmu.txt b/Documentation/perf/thunderx2-pmu.txt new file mode 100644 index 0000000..eb8df9a --- /dev/null +++ b/Documentation/perf/thunderx2-pmu.txt @@ -0,0 +1,60 @@ + +Cavium ThunderX2 SoC Performance Monitoring Unit (PMU UNCORE) +============================================================= + +ThunderX2 SoC PMU consists of independent system wide PMUs such as +Level 3 Cache(L3C) and DDR4 Memory Controller(DMC). + +DMC: There are 8 independent PMUs to capture performance events corresponding +to 8 channels of DDR4 Memory Controller. Each PMU supports upto 4 counters. + +L3C: There are 16 independent PMUs to capture events corresponding to 16 tiles +of L3 cache. Each PMU supports up to 4 counters. + +PMU UNCORE (perf) driver +----------------------- + +The thunderx2-pmu driver registers several perf PMUs for DMC and L3C devices. +Each of the PMU provides description of its available events +and configuration options in sysfs. + see /sys/devices/uncore_<l3c_X/dmc_S_X/. + +S is socket id and X represents channel number. +There are 8 supported channels for DMC and 16 for L3C. +Each channel supports up to 4 counters, which can be measured +simultaneously without event muxing for each channel. + +The "format" directory describes format of the config (event ID). +The "events" directory provides configuration templates for all +supported event types that can be used with perf tool. + +For example, "uncore_dmc_0_0/cnt_cycles/" is an +equivalent of "uncore_dmc_0_0/config=0x1/". + + +Each perf driver also provides a "cpumask" sysfs attribute, which contains a +single CPU ID of the processor which will be used to handle all the PMU events. +It will be the first online CPU of the node of PMU device. + +Example for perf tool use: + +perf stat -a -e \ + uncore_dmc_0_0/cnt_cycles/,\ + uncore_dmc_0_1/cnt_cycles/,\ + uncore_dmc_0_2/cnt_cycles/,\ + uncore_dmc_0_3/cnt_cycles/,\ + uncore_dmc_0_4/cnt_cycles/,\ + uncore_dmc_0_5/cnt_cycles/,\ + uncore_dmc_0_6/cnt_cycles/,\ + uncore_dmc_0_7/cnt_cycles/ \ + sleep 1 + +perf stat -a -e \ + uncore_dmc_0_0/cnt_cycles/,\ + uncore_dmc_0_0/data_txfered/,\ + uncore_dmc_0_0/txn_cycles/,\ + uncore_dmc_0_0/cancelled_read_txn/ \ + sleep 1 + +The driver does not support sampling, therefore "perf record" will +not work. Per-task (without "-a") perf sessions are not supported. -- 1.8.1.4
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