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    Subject[PATCH 4.11 01/58] clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
    Date
    4.11-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Chen-Yu Tsai <wens@csie.org>

    commit 38b8f823864707eb1cf331d2247608c419ed388c upstream.

    The register offset for the lcd1-ch1 clock was incorrectly pointing to
    the lcd0-ch1 clock. This resulted in the lcd0-ch1 clock being disabled
    when the clk core disables unused clocks. This then stops the simplefb
    HDMI output path.

    Reported-by: Bob Ham <rah@settrans.net>
    Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
    Signed-off-by: Chen-Yu Tsai <wens@csie.org>
    Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    --- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
    +++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
    @@ -556,7 +556,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch
    0x12c, 0, 4, 24, 3, BIT(31),
    CLK_SET_RATE_PARENT);
    static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents,
    - 0x12c, 0, 4, 24, 3, BIT(31),
    + 0x130, 0, 4, 24, 3, BIT(31),
    CLK_SET_RATE_PARENT);

    static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1",

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