Messages in this thread | | | From | Linus Walleij <> | Date | Mon, 8 May 2017 23:42:54 +0200 | Subject | Re: [PATCH v2] drm/pl111: Register the clock divider and use it. |
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On Mon, May 8, 2017 at 9:33 PM, Eric Anholt <eric@anholt.net> wrote:
> This is required for the panel to work on bcm911360, where CLCDCLK is > the fixed 200Mhz AXI41 clock. The rate set is still passed up to the > CLCDCLK, for platforms that have a settable rate on that one. > > v2: Set SET_RATE_PARENT (caught by Linus Walleij), depend on > COMMON_CLK. > > Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours, Linus Walleij
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