Messages in this thread | | | From | Stephane Eranian <> | Date | Tue, 30 May 2017 09:39:59 -0700 | Subject | Re: [PATCH 1/2] perf/x86/intel: enable CPU ref_cycles for GP counter |
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On Tue, May 30, 2017 at 2:25 AM, Peter Zijlstra <peterz@infradead.org> wrote: > On Sun, May 28, 2017 at 01:31:09PM -0700, Stephane Eranian wrote: >> Ultimately, I would like to see the watchdog move out of the PMU. That >> is the only sensible solution. >> You just need a resource able to interrupt on NMI or you handle >> interrupt masking in software as has >> been proposed on LKML. > > So even if we do the soft masking, we still need to deal with regions > where the interrupts are disabled. Once an interrupt hits the soft mask > we still hardware mask. > What I was thinking is that you never hardware mask, software always catches the hw interrupts and keeps them pending or deliver them depending on sw mask.
> So to get full and reliable coverage we still need an NMI source. > > I agree that it would be lovely to free up the one counter though. > > > One other approach is running the watchdog off of _any_ PMI, then all we > need to ensure is that PMIs happen semi regularly. There are two cases > where this becomes 'interesting': > > - we have only !sampling events; in this case we have PMIs but at the > max period to properly account for counter overflow. This is too > large a period. We'd have to muck with the max period of at least one > counter. > > - we have _no_ events; in this case we need to somehow schedule an > event anyway. > > It might be possible to deal with both cases by fudging the state of one > of the fixed counters. Never clear the EN bit for that counter and > reduce the max period for that one counter. > > > I think a scheme like that was mentioned before, but I'm also afraid > that it'll turn into quite the mess if we try it. And by its very nature > it adds complexity and therefore risks reducing the reliability of the > thing :/
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