Messages in this thread | | | From | Jassi Brar <> | Date | Wed, 3 May 2017 08:47:44 +0530 | Subject | Re: [PATCH 0/6] mailbox: arm_mhu: add support for subchannels |
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Hi Sudeep,
On Tue, May 2, 2017 at 7:25 PM, Sudeep Holla <sudeep.holla@arm.com> wrote: > Hi Jassi, > > This series adds subchannel support to ARM MHU mailbox controller > driver. Since SCPI never used second slot, we were able to use the > existing driver as is. However, that's changing soon and the new > SCMI protocol under development needs subchannel support. If you > recall when you initially added this driver, I was pushing for some > of these changes like threaded irq. This patch series adds support > for the subchannels on ARM MHU controllers. > There are really no "sub-channels" in the ARM MHU controller. There are exactly three channels that work on 32bit registers. The SET/CLEAR registers are there to prevent races between local and remote firmware, and not to emulate virtual channels operating on single bits. Please remember all 32-bits work together to generate one signal.
You arrived at the "sub-channel" idea only because your protocol uses 1-bit messages. This patchset seems rather regressive - reduce from 2^32 possible signals to mere 32, by bloating the MHU driver.
If it's difficult to see how your protocol can be implemented over existing controller driver, please let me know.
Thanks.
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