lkml.org 
[lkml]   [2017]   [May]   [18]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 4.11 025/114] x86, pmem: Fix cache flushing for iovec write < 8 bytes
    Date
    4.11-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Ben Hutchings <ben.hutchings@codethink.co.uk>

    commit 8376efd31d3d7c44bd05be337adde023cc531fa1 upstream.

    Commit 11e63f6d920d added cache flushing for unaligned writes from an
    iovec, covering the first and last cache line of a >= 8 byte write and
    the first cache line of a < 8 byte write. But an unaligned write of
    2-7 bytes can still cover two cache lines, so make sure we flush both
    in that case.

    Fixes: 11e63f6d920d ("x86, pmem: fix broken __copy_user_nocache ...")
    Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk>
    Signed-off-by: Dan Williams <dan.j.williams@intel.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    arch/x86/include/asm/pmem.h | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    --- a/arch/x86/include/asm/pmem.h
    +++ b/arch/x86/include/asm/pmem.h
    @@ -103,7 +103,7 @@ static inline size_t arch_copy_from_iter

    if (bytes < 8) {
    if (!IS_ALIGNED(dest, 4) || (bytes != 4))
    - arch_wb_cache_pmem(addr, 1);
    + arch_wb_cache_pmem(addr, bytes);
    } else {
    if (!IS_ALIGNED(dest, 8)) {
    dest = ALIGN(dest, boot_cpu_data.x86_clflush_size);

    \
     
     \ /
      Last update: 2017-05-18 14:13    [W:4.271 / U:0.092 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site