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    Subject[PATCH 4.10 013/129] powerpc/perf: Avoid FAB_*_MATCH checks for power9
    Date
    4.10-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>

    commit 78a16d9fc1206e1a484b6ac96348756f3846bfea upstream.

    Since power9 does not support FAB_*_MATCH bits in MMCR1,
    avoid these checks for power9. For this, patch factor out
    code in isa207_get_constraint() to retain these checks
    only for power8.

    Patch also updates the comment in power9-pmu raw event
    encode layout to remove FAB_*_MATCH.

    Finally for power9, patch adds additional check for
    threshold events when adding the thresh mask and value in
    isa207_get_constraint().

    fixes: 7ffd948fae4c ('powerpc/perf: factor out power8 pmu functions')
    fixes: 18201b204286 ('powerpc/perf: power9 raw event format encoding')
    Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
    Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
    Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    arch/powerpc/perf/isa207-common.c | 58 +++++++++++++++++++++++++-------------
    arch/powerpc/perf/power9-pmu.c | 8 +----
    2 files changed, 42 insertions(+), 24 deletions(-)

    --- a/arch/powerpc/perf/isa207-common.c
    +++ b/arch/powerpc/perf/isa207-common.c
    @@ -126,6 +126,28 @@ static unsigned long combine_shift(unsig
    return MMCR1_COMBINE_SHIFT(pmc);
    }

    +static inline bool event_is_threshold(u64 event)
    +{
    + return (event >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
    +}
    +
    +static bool is_thresh_cmp_valid(u64 event)
    +{
    + unsigned int cmp, exp;
    +
    + /*
    + * Check the mantissa upper two bits are not zero, unless the
    + * exponent is also zero. See the THRESH_CMP_MANTISSA doc.
    + */
    + cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
    + exp = cmp >> 7;
    +
    + if (exp && (cmp & 0x60) == 0)
    + return false;
    +
    + return true;
    +}
    +
    int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
    {
    unsigned int unit, pmc, cache, ebb;
    @@ -192,28 +214,26 @@ int isa207_get_constraint(u64 event, uns
    value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
    }

    - /*
    - * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
    - * the threshold control bits are used for the match value.
    - */
    - if (event_is_fab_match(event)) {
    - mask |= CNST_FAB_MATCH_MASK;
    - value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT);
    + if (cpu_has_feature(CPU_FTR_ARCH_300)) {
    + if (event_is_threshold(event) && is_thresh_cmp_valid(event)) {
    + mask |= CNST_THRESH_MASK;
    + value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
    + }
    } else {
    /*
    - * Check the mantissa upper two bits are not zero, unless the
    - * exponent is also zero. See the THRESH_CMP_MANTISSA doc.
    + * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
    + * the threshold control bits are used for the match value.
    */
    - unsigned int cmp, exp;
    -
    - cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
    - exp = cmp >> 7;
    -
    - if (exp && (cmp & 0x60) == 0)
    - return -1;
    + if (event_is_fab_match(event)) {
    + mask |= CNST_FAB_MATCH_MASK;
    + value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT);
    + } else {
    + if (!is_thresh_cmp_valid(event))
    + return -1;

    - mask |= CNST_THRESH_MASK;
    - value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
    + mask |= CNST_THRESH_MASK;
    + value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
    + }
    }

    if (!pmc && ebb)
    @@ -308,7 +328,7 @@ int isa207_compute_mmcr(u64 event[], int
    * PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
    * the threshold bits are used for the match value.
    */
    - if (event_is_fab_match(event[i])) {
    + if (!cpu_has_feature(CPU_FTR_ARCH_300) && event_is_fab_match(event[i])) {
    mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) &
    EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT;
    } else {
    --- a/arch/powerpc/perf/power9-pmu.c
    +++ b/arch/powerpc/perf/power9-pmu.c
    @@ -22,7 +22,7 @@
    * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
    * | | [ ] [ ] [ thresh_cmp ] [ thresh_ctl ]
    * | | | | |
    - * | | *- IFM (Linux) | thresh start/stop OR FAB match -*
    + * | | *- IFM (Linux) | thresh start/stop -*
    * | *- BHRB (Linux) *sm
    * *- EBB (Linux)
    *
    @@ -50,11 +50,9 @@
    * MMCR1[31] = pmc4combine[1]
    *
    * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
    - * # PM_MRK_FAB_RSP_MATCH
    - * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
    + * MMCR1[20:27] = thresh_ctl
    * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
    - * # PM_MRK_FAB_RSP_MATCH_CYC
    - * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
    + * MMCR1[20:27] = thresh_ctl
    * else
    * MMCRA[48:55] = thresh_ctl (THRESH START/END)
    *

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