Messages in this thread | | | Date | Wed, 5 Apr 2017 14:52:26 -0700 | From | Stephen Boyd <> | Subject | Re: [PATCH v2 2/2] clk: stm32f4: fix timeout management for pll and ready gate |
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On 03/16, gabriel.fernandez@st.com wrote: > From: Gabriel Fernandez <gabriel.fernandez@st.com> > > Use a classic polling to test bit ready. > And the shift of the bit ready of LSE & LSI were wrongs. > > Fixes: 861adc44d290 ("clk: stm32f4: Add LSI & LSE clocks") > > Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> > ---
Applied to clk-next
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