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SubjectRe: [PATCH] clk: tegra: fix SS control on PLL enable/disable
On 04/20, Peter De Schrijver wrote:
> PLL SS was only controlled when setting the PLL rate, not when the PLL
> itself is enabled or disabled. This means that if the PLL rate was set
> before the PLL is enabled, SS will not be enabled, even when configured.
> Signed-off-by: Peter De Schrijver <>

Fixes tag? Or this isn't a problem right now, just future fix?

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