Messages in this thread Patch in this message | | | Date | Wed, 19 Apr 2017 03:10:25 -0700 | From | tip-bot for Borislav Petkov <> | Subject | [tip:ras/core] x86/mce: Check MCi_STATUS[MISCV] for usable addr on Intel only |
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Commit-ID: c6a9583fb41c8bd017f643d5bc90a0fe0a92fe43 Gitweb: http://git.kernel.org/tip/c6a9583fb41c8bd017f643d5bc90a0fe0a92fe43 Author: Borislav Petkov <bp@suse.de> AuthorDate: Tue, 18 Apr 2017 20:39:24 +0200 Committer: Thomas Gleixner <tglx@linutronix.de> CommitDate: Wed, 19 Apr 2017 12:04:46 +0200
x86/mce: Check MCi_STATUS[MISCV] for usable addr on Intel only
mce_usable_address() does a bunch of basic sanity checks to verify whether the address reported with the error is usable for further processing. However, we do check MCi_STATUS[MISCV] and that is not needed on AMD as that bit says that there's additional information about the logged error in the MCi_MISCj banks.
But we don't need that to know whether the address is usable - we only need to know whether the physical address is valid - i.e., ADDRV.
On Intel the MISCV bit is needed to perform additional checks to determine whether the reported address is a physical one, etc.
Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Yazen Ghannam <yazen.ghannam@amd.com> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/20170418183924.6agjkebilwqj26or@pd.tnic Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
--- arch/x86/kernel/cpu/mcheck/mce.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index 9d41ec8..4a29f74 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -491,17 +491,22 @@ static void mce_report_event(struct pt_regs *regs) */ static int mce_usable_address(struct mce *m) { - if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) + if (!(m->status & MCI_STATUS_ADDRV)) return 0; /* Checks after this one are Intel-specific: */ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) return 1; + if (!(m->status & MCI_STATUS_MISCV)) + return 0; + if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) return 0; + if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) return 0; + return 1; }
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