Messages in this thread | | | Date | Tue, 11 Apr 2017 15:15:59 +0200 | From | Jesper Nilsson <> | Subject | Re: [PATCH v3 08/32] cris: include default ioremap_nopost() implementation |
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On Tue, Apr 11, 2017 at 01:28:48PM +0100, Lorenzo Pieralisi wrote: > The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting") > mandate non-posted configuration transactions. As further highlighted in > the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the > Enhanced Configuration Access Mechanism"), through ECAM and > ECAM-derivative configuration mechanism, the memory mapped transactions > from the host CPU into Configuration Requests on the PCI express fabric > may create ordering problems for software because writes to memory > address are typically posted transactions (unless the architecture can > enforce through virtual address mapping non-posted write transactions > behaviour) but writes to Configuration Space are not posted on the PCI > express fabric. > > Include the asm-generic ioremap_nopost() implementation (currently > falling back to ioremap_nocache()) to provide a non-posted writes > ioremap interface to kernel subsystems. > > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> > Cc: Niklas Cassel <nks@flawful.org> > Cc: Bjorn Helgaas <bhelgaas@google.com>
For the CRIS-part:
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
/^JN - Jesper Nilsson -- Jesper Nilsson -- jesper.nilsson@axis.com
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