Messages in this thread | | | Date | Mon, 10 Apr 2017 12:34:05 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH v1] x86/mce: enable PPIN for Knights Landing/Mill |
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On Sat, Apr 08, 2017 at 07:20:04PM +0200, Piotr Luc wrote: > Intel Xeon Phi processors (KNL and KNM) do support PPIN as well, so we > add their CPUIDs to the whitelist of supported processors. > PPIN is a unique number that allows to determine origin of the CPU, > from now on will be logged when an mce error occur. > > Signed-off-by: Piotr Luc <piotr.luc@intel.com> > --- > arch/x86/kernel/cpu/mcheck/mce_intel.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c > index 190b3e6..f1c44c3 100644 > --- a/arch/x86/kernel/cpu/mcheck/mce_intel.c > +++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c > @@ -481,6 +481,8 @@ static void intel_ppin_init(struct cpuinfo_x86 *c) > case INTEL_FAM6_BROADWELL_XEON_D: > case INTEL_FAM6_BROADWELL_X: > case INTEL_FAM6_SKYLAKE_X: > + case INTEL_FAM6_XEON_PHI_KNL: > + case INTEL_FAM6_XEON_PHI_KNM: > if (rdmsrl_safe(MSR_PPIN_CTL, &val)) > return; > > --
Applied, thanks.
-- Regards/Gruss, Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
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