Messages in this thread | | | Date | Fri, 24 Mar 2017 09:16:02 +0100 | From | Peter Zijlstra <> | Subject | Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI |
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On Thu, Mar 23, 2017 at 03:23:03PM -0700, Andi Kleen wrote: > On Thu, Mar 23, 2017 at 09:31:38PM +0100, Peter Zijlstra wrote: > > On Thu, Mar 23, 2017 at 11:25:49AM -0700, kan.liang@intel.com wrote: > > > From: Kan Liang <Kan.liang@intel.com> > > > > > > When setting FREEZE_WHILE_SMM bit in IA32_DEBUGCTL, all performance > > > counters will be effected. There is no way to do per-counter freeze > > > on smi. So it should not use the per-event interface (e.g. ioctl or > > > event attribute) to set FREEZE_WHILE_SMM bit. > > > > > > Adds sysfs entry /sys/device/cpu/freeze_on_smi to set FREEZE_WHILE_SMM > > > bit in IA32_DEBUGCTL. When set, freezes perfmon and trace messages > > > while in SMM. > > > Value has to be 0 or 1. It will be applied to all possible cpus. > > > > So is there ever a good reason to not set this? > > That means SMIs become invisible to most performance counters. > > I don't think that's a good default. If the SMI takes 1% of my > cycles I want to see it. > > The masking trick is mainly useful when doing --smi-cost
Changelog should spell this out though. It adds a knob, so it should say why it needs be a knob.
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