Messages in this thread | | | Subject | Re: [PATCH 4/7] clk: tegra: remove non-existing pll_m_out1 clock | From | Mikko Perttunen <> | Date | Thu, 23 Feb 2017 10:17:02 +0200 |
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Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
On 22.02.2017 17:13, Peter De Schrijver wrote: > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> > --- > drivers/clk/tegra/clk-tegra210.c | 5 ----- > 1 file changed, 5 deletions(-) > > diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c > index 7bda8ba..b7ef8a7 100644 > --- a/drivers/clk/tegra/clk-tegra210.c > +++ b/drivers/clk/tegra/clk-tegra210.c > @@ -2115,7 +2115,6 @@ static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv) > [tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true }, > [tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true }, > [tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true }, > - [tegra_clk_pll_m_out1] = { .dt_id = TEGRA210_CLK_PLL_M_OUT1, .present = true }, > [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true }, > [tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true }, > [tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true }, > @@ -2229,7 +2228,6 @@ static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv) > { .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 }, > { .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 }, > { .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M }, > - { .con_id = "pll_m_out1", .dt_id = TEGRA210_CLK_PLL_M_OUT1 }, > { .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X }, > { .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 }, > { .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U }, > @@ -2404,9 +2402,6 @@ static void __init tegra210_pll_init(void __iomem *clk_base, > clk_register_clkdev(clk, "pll_mb", NULL); > clks[TEGRA210_CLK_PLL_MB] = clk; > > - clk_register_clkdev(clk, "pll_m_out1", NULL); > - clks[TEGRA210_CLK_PLL_M_OUT1] = clk; > - > /* PLLM_UD */ > clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", > CLK_SET_RATE_PARENT, 1, 1); >
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