Messages in this thread | | | Subject | Re: [PATCH V2] iommu/amd - Set the device table entry PPR bit for IOMMU V2 devices | From | Gary R Hook <> | Date | Wed, 20 Dec 2017 13:50:47 -0600 |
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On 12/20/2017 01:02 PM, Alex Williamson wrote: > On Tue, 19 Dec 2017 16:15:41 -0600 > Gary R Hook <gary.hook@amd.com> wrote: > >> The AMD IOMMU specification Rev 3.00 (December 2016) introduces a >> new Enhanced PPR Handling Support (EPHSup) bit in the MMIO register >> offset 0030h (IOMMU Extended Feature Register). >> >> When EPHSup=1, the IOMMU hardware requires the PPR bit of the >> device table entry (DTE) to be set in order to support PPR for a >> particular endpoint device. >> >> Please see https://support.amd.com/TechDocs/48882_IOMMU.pdf for >> this revision of the AMD IOMMU specification. >> >> Signed-off-by: Gary R Hook <gary.hook@amd.com> >> --- >> 0 files changed > > Hmm, something funky there, but looks fine otherwise. Applied to > v4.16-iommu/amd. Thanks, > > Alex >
Thanks. I have no clue why it says "0 files changed". I just looked again and it seems fine here.
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