Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Fri, 15 Dec 2017 09:01:50 +0100 | Subject | Re: [PATCH v3 2/2] drm: rcar-du: calculate DPLLCR to be more small jitter |
| |
Hi Morimoto-san,
On Fri, Dec 15, 2017 at 2:24 AM, Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> wrote: > From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> > In general, PLL has VCO (= Voltage controlled oscillator), > one of the very important electronic feature called as "jitter" > is related to this VCO. > In academic generalism, VCO should be maximum to be more small jitter. > In high frequency clock, jitter will be large impact. > Thus, selecting Hi VCO is general theory.
Thanks for your patch!
> One note here is that it should be 2000 < fvco < 4096MHz
2000 Hz? (else it could be misinterpreted that MHz applies to both values).
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
| |