Messages in this thread | | | Subject | Re: [PATCH v1] clk: tegra20: Add 216 MHz entry for PLL_X | From | Dmitry Osipenko <> | Date | Wed, 13 Dec 2017 00:37:28 +0300 |
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On 12.12.2017 18:17, Peter De Schrijver wrote: > On Tue, Dec 12, 2017 at 03:08:08PM +0300, Dmitry Osipenko wrote: >> On 12.12.2017 13:02, Peter De Schrijver wrote: >>> On Mon, Dec 11, 2017 at 09:50:09PM +0300, Dmitry Osipenko wrote: >>>> The cpufreq driver uses 216 MHz as the lowest CPU clock frequency, but >>>> clock driver doesn't provide that rate, so the requested clock is rounded >>>> up to 312 MHz. Let's add entry for 216 MHz to match with cpufreq. >>>> >>> >>> This seems odd. If there's no table entry, _calc_rate should kick in and >>> calculate the parameters for 216MHz. Any idea why this is not happening? >> >> Actually, it is happening. Please ignore this patch. >> >> If PLL's rate could be calculated, why do we need the predefined tables? > > The algorithm to calculate the PLL parameters is rather crude. It will > favour undershooting the rate rather than overshooting. This is fine for > DVFS usecases when you want to avoid a too high clock rate, but not good > for eg display or memory, where as close as match as possible is needed. Okay, thank you for the clarification.
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