Messages in this thread | | | From | Luc Van Oostenryck <> | Date | Thu, 9 Nov 2017 22:46:50 +0100 | Subject | Re: [patches] [PATCH 0/2] riscv: pass endianness and machine size to sparse |
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On Thu, Nov 9, 2017 at 10:36 PM, Palmer Dabbelt <palmer@sifive.com> wrote: > On Wed, 08 Nov 2017 21:53:52 PST (-0800), luc.vanoostenryck@gmail.com wrote: >> The goal of these two patches is to ass endianness and machine >> size info to sparse so that sparse can emit correct diagnostics >> even when the endianness and machine size doesn't correspond to >> sparse's defaults. >> >> Luc Van Oostenryck (2): >> riscv: pass endianness info to sparse >> riscv: pass machine size to sparse >> >> arch/riscv/Makefile | 4 ++++ >> 1 file changed, 4 insertions(+) > > Thanks! I'll take these into the RISC-V tree.
Well, better to hold one because someone has asked to treat the problem in a generic way (the same problem exist on other archs) and I certainly think it's indeed better.
I'll sent a newer patch in a day or two.
Sorry for this, -- Luc Van Oostenryck
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