Messages in this thread Patch in this message | | | From | Stephane Eranian <> | Subject | [PATCH v3 2/5] perf/x86: add PERF_SAMPLE_SKID_IP support for X86 PEBS | Date | Tue, 7 Nov 2017 23:56:34 -0800 |
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This patch adds support for SKID_IP for Intel x86 processors when PEBS mode is enabled.
Signed-off-by: Stephane Eranian <eranian@google.com> --- arch/x86/events/intel/ds.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 3674a4b6f8bd..52866a470b0d 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -1190,6 +1190,13 @@ static void setup_pebs_sample_data(struct perf_event *event, x86_pmu.intel_cap.pebs_format >= 1) data->addr = pebs->dla; + /* + * unmodified, skid IP which is guaranteed to be the next + * dynamic instruction + */ + if (sample_type & PERF_SAMPLE_SKID_IP) + data->skid_ip = pebs->ip; + if (x86_pmu.intel_cap.pebs_format >= 2) { /* Only set the TSX weight when no memory weight. */ if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll) -- 2.7.4
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