Messages in this thread | | | Subject | Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA | From | Yixun Lan <> | Date | Mon, 6 Nov 2017 17:51:02 +0800 |
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Hi Jerome:
On 11/06/17 17:10, Jerome Brunet wrote: > On Mon, 2017-11-06 at 15:52 +0800, Yixun Lan wrote: >> According to the datasheet, in Meson-GXBB/GXL series, >> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], >> while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10]. >> >> Test passed at gxl_skt dev board. > I think this refer to a board naming used in amlogic vendor kernel ? > Would you mind telling what it is ? >
sorry, it's actually tested at gxl-s905x-p212 board.
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