lkml.org 
[lkml]   [2017]   [Nov]   [26]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
Date
SubjectRe: [PATCH v2] x86/entry: Fix assumptions that the HW TSS is at the beginning of cpu_tss
On Sun, Nov 26, 2017 at 5:48 AM, Ingo Molnar <mingo@kernel.org> wrote:
>
> * Dave Hansen <dave.hansen@intel.com> wrote:
>
>> On 11/10/2017 08:05 PM, Andy Lutomirski wrote:
>> > -struct tss_struct doublefault_tss __cacheline_aligned = {
>> > - .x86_tss = {
>> > - .sp0 = STACK_START,
>> > - .ss0 = __KERNEL_DS,
>> > - .ldt = 0,
>> ...
>> > +struct x86_hw_tss doublefault_tss __cacheline_aligned = {
>> > + .sp0 = STACK_START,
>> > + .ss0 = __KERNEL_DS,
>> > + .ldt = 0,
>> > + .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
>>
>> FWIW, I really like the trend of renaming the hardware structures in
>> such a way that it's clear that they *are* hardware structures.
>>
>> It might also be nice to reference the relevant SDM sections on the
>> topic, or even to include a comment along the lines of how it get used.
>> This chunk from the SDM is particularly relevant:
>>
>> "The TSS holds information important to 64-bit mode and that is not
>> directly related to the task-switch mechanism."
>
> That makes sense - I've updated this patch with the following description added to
> struct x86_hw_tss:

I've folded this in along with all the reviews so far, and a few misc
fixes from Boris' review. I was planning to resend the whole series
today after I track down the kbuild error. Does that sound good?

\
 
 \ /
  Last update: 2017-11-26 16:42    [W:0.052 / U:2.796 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site