Messages in this thread | | | Date | Thu, 2 Nov 2017 01:12:05 -0700 | From | Stephen Boyd <> | Subject | Re: [PATCH v2 2/4] clk: mediatek: add the option for determining PLL source clock |
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On 10/05, sean.wang@mediatek.com wrote: > From: Chen Zhong <chen.zhong@mediatek.com> > > Since the previous setup always sets the PLL using crystal 26MHz, this > doesn't always happen in every MediaTek platform. So the patch added > flexibility for assigning extra member for determining the PLL source > clock. > > Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> > Signed-off-by: Sean Wang <sean.wang@mediatek.com> > ---
Applied to clk-next
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