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    Subject[PATCH v18 6/6] drm/i915/gvt: Dmabuf support for GVT-g
    Date
    This patch introduces a guest's framebuffer sharing mechanism based on
    dma-buf subsystem. With this sharing mechanism, guest's framebuffer can
    be shared between guest VM and host.

    v17:
    - modify VFIO_DEVICE_GET_GFX_DMABUF interface. (Alex)

    v16:
    - add x_hot and y_hot. (Gerd)
    - add flag validation for VFIO_DEVICE_GET_GFX_DMABUF. (Alex)
    - rebase 4.14.0-rc6.

    v15:
    - add VFIO_DEVICE_GET_GFX_DMABUF ABI. (Gerd)
    - add intel_vgpu_dmabuf_cleanup() to clean up the vGPU's dmabuf. (Gerd)

    v14:
    - add PROBE, DMABUF and REGION flags. (Alex)

    v12:
    - refine the lifecycle of dmabuf.

    v9:
    - remove dma-buf management. (Alex)
    - track the dma-buf create and release in kernel mode. (Gerd) (Daniel)

    v8:
    - refine the dma-buf ioctl definition.(Alex)
    - add a lock to protect the dmabuf list. (Alex)

    v7:
    - release dma-buf related allocations in dma-buf's associated release
    function. (Alex)
    - refine ioctl interface for querying plane info or create dma-buf.
    (Alex)

    v6:
    - align the dma-buf life cycle with the vfio device. (Alex)
    - add the dma-buf related operations in a separate patch. (Gerd)
    - i915 related changes. (Chris)

    v5:
    - fix bug while checking whether the gem obj is gvt's dma-buf when user
    change caching mode or domains. Add a helper function to do it.
    (Xiaoguang)
    - add definition for the query plane and create dma-buf. (Xiaoguang)

    v4:
    - fix bug while checking whether the gem obj is gvt's dma-buf when set
    caching mode or doamins. (Xiaoguang)

    v3:
    - declare a new flag I915_GEM_OBJECT_IS_GVT_DMABUF in drm_i915_gem_object
    to represent the gem obj for gvt's dma-buf. The tiling mode, caching
    mode and domains can not be changed for this kind of gem object. (Alex)
    - change dma-buf related information to be more generic. So other vendor
    can use the same interface. (Alex)

    v2:
    - create a management fd for dma-buf operations. (Alex)
    - alloc gem object's backing storage in gem obj's get_pages() callback.
    (Chris)

    Signed-off-by: Tina Zhang <tina.zhang@intel.com>
    Cc: Alex Williamson <alex.williamson@redhat.com>
    Cc: Chris Wilson <chris@chris-wilson.co.uk>
    Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
    Cc: Gerd Hoffmann <kraxel@redhat.com>
    ---
    drivers/gpu/drm/i915/gvt/Makefile | 2 +-
    drivers/gpu/drm/i915/gvt/dmabuf.c | 523 +++++++++++++++++++++++++++++++++
    drivers/gpu/drm/i915/gvt/dmabuf.h | 67 +++++
    drivers/gpu/drm/i915/gvt/gvt.c | 2 +
    drivers/gpu/drm/i915/gvt/gvt.h | 11 +
    drivers/gpu/drm/i915/gvt/hypercall.h | 2 +
    drivers/gpu/drm/i915/gvt/kvmgt.c | 53 ++++
    drivers/gpu/drm/i915/gvt/mpt.h | 30 ++
    drivers/gpu/drm/i915/gvt/vgpu.c | 5 +-
    drivers/gpu/drm/i915/i915_gem_object.h | 2 +
    10 files changed, 695 insertions(+), 2 deletions(-)
    create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.c
    create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.h

    diff --git a/drivers/gpu/drm/i915/gvt/Makefile b/drivers/gpu/drm/i915/gvt/Makefile
    index 54d70df..cae06c1 100644
    --- a/drivers/gpu/drm/i915/gvt/Makefile
    +++ b/drivers/gpu/drm/i915/gvt/Makefile
    @@ -2,7 +2,7 @@ GVT_DIR := gvt
    GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
    interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \
    execlist.o scheduler.o sched_policy.o render.o cmd_parser.o debugfs.o \
    - fb_decoder.o
    + fb_decoder.o dmabuf.o

    ccflags-y += -I$(src) -I$(src)/$(GVT_DIR)
    i915-y += $(addprefix $(GVT_DIR)/, $(GVT_SOURCE))
    diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c
    new file mode 100644
    index 0000000..190710c
    --- /dev/null
    +++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
    @@ -0,0 +1,523 @@
    +/*
    + * Copyright 2017 Intel Corporation. All rights reserved.
    + *
    + * Permission is hereby granted, free of charge, to any person obtaining a
    + * copy of this software and associated documentation files (the "Software"),
    + * to deal in the Software without restriction, including without limitation
    + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
    + * and/or sell copies of the Software, and to permit persons to whom the
    + * Software is furnished to do so, subject to the following conditions:
    + *
    + * The above copyright notice and this permission notice (including the next
    + * paragraph) shall be included in all copies or substantial portions of the
    + * Software.
    + *
    + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
    + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
    + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
    + * DEALINGS IN THE SOFTWARE.
    + *
    + * Authors:
    + * Zhiyuan Lv <zhiyuan.lv@intel.com>
    + *
    + * Contributors:
    + * Xiaoguang Chen
    + * Tina Zhang <tina.zhang@intel.com>
    + */
    +
    +#include <linux/dma-buf.h>
    +#include <drm/drmP.h>
    +#include <linux/vfio.h>
    +
    +#include "i915_drv.h"
    +#include "gvt.h"
    +
    +#define GEN8_DECODE_PTE(pte) (pte & GENMASK_ULL(63, 12))
    +
    +static int vgpu_gem_get_pages(
    + struct drm_i915_gem_object *obj)
    +{
    + struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
    + struct sg_table *st;
    + struct scatterlist *sg;
    + int i, ret;
    + gen8_pte_t __iomem *gtt_entries;
    + struct intel_vgpu_fb_info *fb_info;
    +
    + fb_info = (struct intel_vgpu_fb_info *)obj->gvt_info;
    + if (WARN_ON(!fb_info))
    + return -ENODEV;
    +
    + st = kmalloc(sizeof(*st), GFP_KERNEL);
    + if (unlikely(!st))
    + return -ENOMEM;
    +
    + ret = sg_alloc_table(st, fb_info->size, GFP_KERNEL);
    + if (ret) {
    + kfree(st);
    + return ret;
    + }
    + gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
    + (fb_info->start >> PAGE_SHIFT);
    + for_each_sg(st->sgl, sg, fb_info->size, i) {
    + sg->offset = 0;
    + sg->length = PAGE_SIZE;
    + sg_dma_address(sg) =
    + GEN8_DECODE_PTE(readq(&gtt_entries[i]));
    + sg_dma_len(sg) = PAGE_SIZE;
    + }
    +
    + __i915_gem_object_set_pages(obj, st, PAGE_SIZE);
    +
    + return 0;
    +}
    +
    +static void vgpu_gem_put_pages(struct drm_i915_gem_object *obj,
    + struct sg_table *pages)
    +{
    + sg_free_table(pages);
    + kfree(pages);
    +}
    +
    +static void dmabuf_gem_object_free(struct kref *kref)
    +{
    + struct intel_vgpu_dmabuf_obj *obj =
    + container_of(kref, struct intel_vgpu_dmabuf_obj, kref);
    + struct intel_vgpu *vgpu = obj->vgpu;
    + struct list_head *pos;
    +
    + struct intel_vgpu_dmabuf_obj *dmabuf_obj;
    +
    + list_for_each(pos, &vgpu->dmabuf_obj_list_head) {
    + dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj,
    + list);
    + if (dmabuf_obj == obj) {
    + idr_remove(&vgpu->object_idr, dmabuf_obj->dmabuf_id);
    + kfree(dmabuf_obj->info);
    + kfree(dmabuf_obj);
    + list_del(pos);
    + break;
    + }
    + }
    +}
    +
    +
    +static inline void dmabuf_obj_get(struct intel_vgpu_dmabuf_obj *obj)
    +{
    + kref_get(&obj->kref);
    +}
    +
    +static inline void dmabuf_obj_put(struct intel_vgpu_dmabuf_obj *obj)
    +{
    + kref_put(&obj->kref, dmabuf_gem_object_free);
    +}
    +
    +static void vgpu_gem_release(struct drm_i915_gem_object *gem_obj)
    +{
    +
    + struct intel_vgpu_fb_info *fb_info = gem_obj->gvt_info;
    + struct intel_vgpu_dmabuf_obj *obj = fb_info->obj;
    + struct intel_vgpu *vgpu = obj->vgpu;
    +
    + mutex_lock(&vgpu->dmabuf_lock);
    + gem_obj->base.dma_buf = NULL;
    + dmabuf_obj_put(obj);
    + intel_gvt_hypervisor_put_vfio_device(vgpu);
    + mutex_unlock(&vgpu->dmabuf_lock);
    +}
    +
    +static const struct drm_i915_gem_object_ops intel_vgpu_gem_ops = {
    + .flags = I915_GEM_OBJECT_IS_PROXY,
    + .get_pages = vgpu_gem_get_pages,
    + .put_pages = vgpu_gem_put_pages,
    + .release = vgpu_gem_release,
    +};
    +
    +static struct drm_i915_gem_object *vgpu_create_gem(struct drm_device *dev,
    + struct intel_vgpu_fb_info *info)
    +{
    + struct drm_i915_private *dev_priv = to_i915(dev);
    + struct drm_i915_gem_object *obj;
    +
    + obj = i915_gem_object_alloc(dev_priv);
    + if (obj == NULL)
    + return NULL;
    +
    + drm_gem_private_object_init(dev, &obj->base,
    + info->size << PAGE_SHIFT);
    + i915_gem_object_init(obj, &intel_vgpu_gem_ops);
    +
    + obj->base.read_domains = I915_GEM_DOMAIN_GTT;
    + obj->base.write_domain = 0;
    + if (IS_SKYLAKE(dev_priv)) {
    + unsigned int tiling_mode = 0;
    + unsigned int stride = 0;
    +
    + switch (info->drm_format_mod << 10) {
    + case PLANE_CTL_TILED_LINEAR:
    + tiling_mode = I915_TILING_NONE;
    + break;
    + case PLANE_CTL_TILED_X:
    + tiling_mode = I915_TILING_X;
    + stride = info->stride;
    + break;
    + case PLANE_CTL_TILED_Y:
    + tiling_mode = I915_TILING_Y;
    + stride = info->stride;
    + break;
    + default:
    + gvt_dbg_core("not supported tiling mode\n");
    + }
    + obj->tiling_and_stride = tiling_mode | stride;
    + } else {
    + obj->tiling_and_stride = info->drm_format_mod ?
    + I915_TILING_X : 0;
    + }
    +
    + return obj;
    +}
    +
    +static int vgpu_get_plane_info(struct drm_device *dev,
    + struct intel_vgpu *vgpu,
    + struct intel_vgpu_fb_info *info,
    + int plane_id)
    +{
    + struct drm_i915_private *dev_priv = to_i915(dev);
    + struct intel_vgpu_primary_plane_format p;
    + struct intel_vgpu_cursor_plane_format c;
    + int ret;
    +
    + if (plane_id == DRM_PLANE_TYPE_PRIMARY) {
    + ret = intel_vgpu_decode_primary_plane(vgpu, &p);
    + if (ret)
    + return ret;
    + info->start = p.base;
    + info->start_gpa = p.base_gpa;
    + info->width = p.width;
    + info->height = p.height;
    + info->stride = p.stride;
    + info->drm_format = p.drm_format;
    + info->drm_format_mod = p.tiled;
    + info->size = (((p.stride * p.height * p.bpp) / 8) +
    + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
    + } else if (plane_id == DRM_PLANE_TYPE_CURSOR) {
    + ret = intel_vgpu_decode_cursor_plane(vgpu, &c);
    + if (ret)
    + return ret;
    + info->start = c.base;
    + info->start_gpa = c.base_gpa;
    + info->width = c.width;
    + info->height = c.height;
    + info->stride = c.width * (c.bpp / 8);
    + info->drm_format = c.drm_format;
    + info->drm_format_mod = 0;
    + info->x_pos = c.x_pos;
    + info->y_pos = c.y_pos;
    +
    + /* The invalid cursor hotspot value is delivered to host
    + * until we find a way to get the cursor hotspot info of
    + * guest OS.
    + */
    + info->x_hot = UINT_MAX;
    + info->y_hot = UINT_MAX;
    + info->size = (((info->stride * c.height * c.bpp) / 8)
    + + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
    + } else {
    + gvt_vgpu_err("invalid plane id:%d\n", plane_id);
    + return -EINVAL;
    + }
    +
    + if (info->size == 0) {
    + gvt_vgpu_err("fb size is zero\n");
    + return -EINVAL;
    + }
    +
    + if (info->start & (PAGE_SIZE - 1)) {
    + gvt_vgpu_err("Not aligned fb address:0x%llx\n", info->start);
    + return -EFAULT;
    + }
    + if (((info->start >> PAGE_SHIFT) + info->size) >
    + ggtt_total_entries(&dev_priv->ggtt)) {
    + gvt_vgpu_err("Invalid GTT offset or size\n");
    + return -EFAULT;
    + }
    +
    + if (!intel_gvt_ggtt_validate_range(vgpu, info->start, info->size)) {
    + gvt_vgpu_err("invalid gma addr\n");
    + return -EFAULT;
    + }
    +
    + return 0;
    +}
    +
    +static struct intel_vgpu_dmabuf_obj *
    +pick_dmabuf_by_info(struct intel_vgpu *vgpu,
    + struct intel_vgpu_fb_info *latest_info)
    +{
    + struct list_head *pos;
    + struct intel_vgpu_fb_info *fb_info;
    + struct intel_vgpu_dmabuf_obj *dmabuf_obj = NULL;
    + struct intel_vgpu_dmabuf_obj *ret = NULL;
    +
    + list_for_each(pos, &vgpu->dmabuf_obj_list_head) {
    + dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj,
    + list);
    + if ((dmabuf_obj == NULL) ||
    + (dmabuf_obj->info == NULL))
    + continue;
    +
    + fb_info = (struct intel_vgpu_fb_info *)dmabuf_obj->info;
    + if ((fb_info->start == latest_info->start) &&
    + (fb_info->start_gpa == latest_info->start_gpa) &&
    + (fb_info->size == latest_info->size) &&
    + (fb_info->drm_format_mod == latest_info->drm_format_mod) &&
    + (fb_info->drm_format == latest_info->drm_format) &&
    + (fb_info->width == latest_info->width) &&
    + (fb_info->height == latest_info->height)) {
    + ret = dmabuf_obj;
    + break;
    + }
    + }
    +
    + return ret;
    +}
    +
    +static struct intel_vgpu_dmabuf_obj *
    +pick_dmabuf_by_num(struct intel_vgpu *vgpu, u32 id)
    +{
    + struct list_head *pos;
    + struct intel_vgpu_dmabuf_obj *dmabuf_obj = NULL;
    + struct intel_vgpu_dmabuf_obj *ret = NULL;
    +
    + list_for_each(pos, &vgpu->dmabuf_obj_list_head) {
    + dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj,
    + list);
    + if (!dmabuf_obj)
    + continue;
    +
    + if (dmabuf_obj->dmabuf_id == id) {
    + ret = dmabuf_obj;
    + break;
    + }
    + }
    +
    + return ret;
    +}
    +
    +static void update_fb_info(struct vfio_device_gfx_plane_info *gvt_dmabuf,
    + struct intel_vgpu_fb_info *fb_info)
    +{
    + gvt_dmabuf->drm_format = fb_info->drm_format;
    + gvt_dmabuf->width = fb_info->width;
    + gvt_dmabuf->height = fb_info->height;
    + gvt_dmabuf->stride = fb_info->stride;
    + gvt_dmabuf->size = fb_info->size;
    + gvt_dmabuf->x_pos = fb_info->x_pos;
    + gvt_dmabuf->y_pos = fb_info->y_pos;
    + gvt_dmabuf->x_hot = fb_info->x_hot;
    + gvt_dmabuf->y_hot = fb_info->y_hot;
    +}
    +
    +int intel_vgpu_query_plane(struct intel_vgpu *vgpu, void *args)
    +{
    + struct drm_device *dev = &vgpu->gvt->dev_priv->drm;
    + struct vfio_device_gfx_plane_info *gfx_plane_info = args;
    + struct intel_vgpu_dmabuf_obj *dmabuf_obj;
    + struct intel_vgpu_fb_info fb_info;
    + int ret = 0;
    +
    + if (gfx_plane_info->flags == (VFIO_GFX_PLANE_TYPE_DMABUF |
    + VFIO_GFX_PLANE_TYPE_PROBE))
    + return ret;
    + else if ((gfx_plane_info->flags & ~VFIO_GFX_PLANE_TYPE_DMABUF) ||
    + (!gfx_plane_info->flags))
    + return -EINVAL;
    +
    + ret = vgpu_get_plane_info(dev, vgpu, &fb_info,
    + gfx_plane_info->drm_plane_type);
    + if (ret != 0)
    + goto out;
    +
    + mutex_lock(&vgpu->dmabuf_lock);
    + /* If exists, pick up the exposed dmabuf_obj */
    + dmabuf_obj = pick_dmabuf_by_info(vgpu, &fb_info);
    + if (dmabuf_obj) {
    + update_fb_info(gfx_plane_info, &fb_info);
    + gfx_plane_info->dmabuf_id = dmabuf_obj->dmabuf_id;
    +
    + /* This buffer may be released between query_plane ioctl and
    + * get_dmabuf ioctl. Add the refcount to make sure it won't
    + * be released between the two ioctls.
    + */
    + if (!dmabuf_obj->initref) {
    + dmabuf_obj->initref = true;
    + dmabuf_obj_get(dmabuf_obj);
    + }
    + ret = 0;
    + gvt_dbg_dpy("vgpu%d: re-use dmabuf_obj ref %d, id %d\n",
    + vgpu->id, kref_read(&dmabuf_obj->kref),
    + gfx_plane_info->dmabuf_id);
    + mutex_unlock(&vgpu->dmabuf_lock);
    + goto out;
    + }
    +
    + mutex_unlock(&vgpu->dmabuf_lock);
    +
    + /* Need to allocate a new one*/
    + dmabuf_obj = kmalloc(sizeof(struct intel_vgpu_dmabuf_obj), GFP_KERNEL);
    + if (unlikely(!dmabuf_obj)) {
    + gvt_vgpu_err("alloc dmabuf_obj failed\n");
    + ret = -ENOMEM;
    + goto out;
    + }
    +
    + dmabuf_obj->info = kmalloc(sizeof(struct intel_vgpu_fb_info),
    + GFP_KERNEL);
    + if (unlikely(!dmabuf_obj->info)) {
    + gvt_vgpu_err("allocate intel vgpu fb info failed\n");
    + ret = -ENOMEM;
    + goto out_free_dmabuf;
    + }
    + memcpy(dmabuf_obj->info, &fb_info, sizeof(struct intel_vgpu_fb_info));
    +
    + ((struct intel_vgpu_fb_info *)dmabuf_obj->info)->obj = dmabuf_obj;
    +
    + dmabuf_obj->vgpu = vgpu;
    +
    + ret = idr_alloc(&vgpu->object_idr, dmabuf_obj, 1, 0, GFP_NOWAIT);
    + if (ret < 0)
    + goto out_free_info;
    + gfx_plane_info->dmabuf_id = ret;
    + dmabuf_obj->dmabuf_id = ret;
    +
    + dmabuf_obj->initref = true;
    +
    + kref_init(&dmabuf_obj->kref);
    +
    + mutex_lock(&vgpu->dmabuf_lock);
    + if (intel_gvt_hypervisor_get_vfio_device(vgpu)) {
    + gvt_vgpu_err("get vfio device failed\n");
    + mutex_unlock(&vgpu->dmabuf_lock);
    + goto out_free_info;
    + }
    + mutex_unlock(&vgpu->dmabuf_lock);
    +
    + update_fb_info(gfx_plane_info, &fb_info);
    +
    + INIT_LIST_HEAD(&dmabuf_obj->list);
    + mutex_lock(&vgpu->dmabuf_lock);
    + list_add_tail(&dmabuf_obj->list, &vgpu->dmabuf_obj_list_head);
    + mutex_unlock(&vgpu->dmabuf_lock);
    +
    + gvt_dbg_dpy("vgpu%d: %s new dmabuf_obj ref %d, id %d\n", vgpu->id,
    + __func__, kref_read(&dmabuf_obj->kref), ret);
    +
    + return 0;
    +
    +out_free_info:
    + kfree(dmabuf_obj->info);
    +out_free_dmabuf:
    + kfree(dmabuf_obj);
    +out:
    + /* ENODEV means plane isn't ready, which might be a normal case. */
    + return (ret == -ENODEV) ? 0 : ret;
    +}
    +
    +/* To associate an exposed dmabuf with the dmabuf_obj */
    +int intel_vgpu_get_dmabuf(struct intel_vgpu *vgpu, unsigned int dmabuf_id)
    +{
    + struct drm_device *dev = &vgpu->gvt->dev_priv->drm;
    + struct intel_vgpu_dmabuf_obj *dmabuf_obj;
    + struct drm_i915_gem_object *obj;
    + struct dma_buf *dmabuf;
    + int dmabuf_fd;
    + int ret = 0;
    +
    + mutex_lock(&vgpu->dmabuf_lock);
    +
    + dmabuf_obj = pick_dmabuf_by_num(vgpu, dmabuf_id);
    + if (dmabuf_obj == NULL) {
    + gvt_vgpu_err("invalid dmabuf id:%d\n", dmabuf_id);
    + ret = -EINVAL;
    + goto out;
    + }
    +
    + obj = vgpu_create_gem(dev, dmabuf_obj->info);
    + if (obj == NULL) {
    + gvt_vgpu_err("create gvt gem obj failed:%d\n", vgpu->id);
    + ret = -ENOMEM;
    + goto out;
    + }
    +
    + obj->gvt_info = dmabuf_obj->info;
    +
    + dmabuf = i915_gem_prime_export(dev, &obj->base, DRM_CLOEXEC | DRM_RDWR);
    + if (IS_ERR(dmabuf)) {
    + gvt_vgpu_err("export dma-buf failed\n");
    + ret = PTR_ERR(dmabuf);
    + goto out_free_gem;
    + }
    + obj->base.dma_buf = dmabuf;
    +
    + i915_gem_object_put(obj);
    +
    + ret = dma_buf_fd(dmabuf, DRM_CLOEXEC | DRM_RDWR);
    + if (ret < 0) {
    + gvt_vgpu_err("create dma-buf fd failed ret:%d\n", ret);
    + goto out_free_dmabuf;
    + }
    + dmabuf_fd = ret;
    +
    + if (intel_gvt_hypervisor_get_vfio_device(vgpu)) {
    + gvt_vgpu_err("get vfio device failed\n");
    + put_unused_fd(ret);
    + goto out_free_dmabuf;
    + }
    +
    + dmabuf_obj_get(dmabuf_obj);
    +
    + if (dmabuf_obj->initref) {
    + dmabuf_obj->initref = false;
    + dmabuf_obj_put(dmabuf_obj);
    + }
    +
    + mutex_unlock(&vgpu->dmabuf_lock);
    +
    + gvt_dbg_dpy("vgpu%d: dmabuf:%d, dmabuf ref %d, fd:%d\n"
    + " file count: %ld, GEM ref: %d\n",
    + vgpu->id, dmabuf_obj->dmabuf_id,
    + kref_read(&dmabuf_obj->kref),
    + dmabuf_fd,
    + file_count(dmabuf->file),
    + kref_read(&obj->base.refcount));
    +
    + return dmabuf_fd;
    +
    +out_free_dmabuf:
    + dma_buf_put(dmabuf);
    +out_free_gem:
    + i915_gem_object_put(obj);
    +out:
    + mutex_unlock(&vgpu->dmabuf_lock);
    + return ret;
    +}
    +
    +void intel_vgpu_dmabuf_cleanup(struct intel_vgpu *vgpu)
    +{
    + struct list_head *pos, *n;
    + struct intel_vgpu_dmabuf_obj *dmabuf_obj;
    +
    + mutex_lock(&vgpu->dmabuf_lock);
    + list_for_each_safe(pos, n, &vgpu->dmabuf_obj_list_head) {
    + dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj,
    + list);
    + if (dmabuf_obj->initref) {
    + dmabuf_obj->initref = false;
    + dmabuf_obj_put(dmabuf_obj);
    + }
    + }
    + mutex_unlock(&vgpu->dmabuf_lock);
    +}
    diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.h b/drivers/gpu/drm/i915/gvt/dmabuf.h
    new file mode 100644
    index 0000000..5f8f03f
    --- /dev/null
    +++ b/drivers/gpu/drm/i915/gvt/dmabuf.h
    @@ -0,0 +1,67 @@
    +/*
    + * Copyright(c) 2017 Intel Corporation. All rights reserved.
    + *
    + * Permission is hereby granted, free of charge, to any person obtaining a
    + * copy of this software and associated documentation files (the "Software"),
    + * to deal in the Software without restriction, including without limitation
    + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
    + * and/or sell copies of the Software, and to permit persons to whom the
    + * Software is furnished to do so, subject to the following conditions:
    + *
    + * The above copyright notice and this permission notice (including the next
    + * paragraph) shall be included in all copies or substantial portions of the
    + * Software.
    + *
    + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
    + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
    + * SOFTWARE.
    + *
    + * Authors:
    + * Zhiyuan Lv <zhiyuan.lv@intel.com>
    + *
    + * Contributors:
    + * Xiaoguang Chen
    + * Tina Zhang <tina.zhang@intel.com>
    + */
    +
    +#ifndef _GVT_DMABUF_H_
    +#define _GVT_DMABUF_H_
    +#include <linux/vfio.h>
    +
    +struct intel_vgpu_fb_info {
    + __u64 start;
    + __u64 start_gpa;
    + __u64 drm_format_mod;
    + __u32 drm_format; /* drm format of plane */
    + __u32 width; /* width of plane */
    + __u32 height; /* height of plane */
    + __u32 stride; /* stride of plane */
    + __u32 size; /* size of plane in bytes, align on page */
    + __u32 x_pos; /* horizontal position of cursor plane */
    + __u32 y_pos; /* vertical position of cursor plane */
    + __u32 x_hot; /* horizontal position of cursor hotspot */
    + __u32 y_hot; /* vertical position of cursor hotspot */
    + struct intel_vgpu_dmabuf_obj *obj;
    +};
    +
    +/**
    + * struct intel_vgpu_dmabuf_obj- Intel vGPU device buffer object
    + */
    +struct intel_vgpu_dmabuf_obj {
    + struct intel_vgpu *vgpu;
    + struct intel_vgpu_fb_info *info;
    + __u32 dmabuf_id;
    + struct kref kref;
    + bool initref;
    + struct list_head list;
    +};
    +
    +int intel_vgpu_query_plane(struct intel_vgpu *vgpu, void *args);
    +int intel_vgpu_get_dmabuf(struct intel_vgpu *vgpu, unsigned int dmabuf_id);
    +void intel_vgpu_dmabuf_cleanup(struct intel_vgpu *vgpu);
    +
    +#endif
    diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c
    index cef06d5..2b050ff 100644
    --- a/drivers/gpu/drm/i915/gvt/gvt.c
    +++ b/drivers/gpu/drm/i915/gvt/gvt.c
    @@ -181,6 +181,8 @@ static const struct intel_gvt_ops intel_gvt_ops = {
    .vgpu_deactivate = intel_gvt_deactivate_vgpu,
    .gvt_find_vgpu_type = intel_gvt_find_vgpu_type,
    .get_gvt_attrs = intel_get_gvt_attrs,
    + .vgpu_query_plane = intel_vgpu_query_plane,
    + .vgpu_get_dmabuf = intel_vgpu_get_dmabuf,
    };

    /**
    diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
    index c8e496c..8e5a4ea 100644
    --- a/drivers/gpu/drm/i915/gvt/gvt.h
    +++ b/drivers/gpu/drm/i915/gvt/gvt.h
    @@ -47,6 +47,7 @@
    #include "render.h"
    #include "cmd_parser.h"
    #include "fb_decoder.h"
    +#include "dmabuf.h"

    #define GVT_MAX_VGPU 8

    @@ -208,8 +209,16 @@ struct intel_vgpu {
    struct kvm *kvm;
    struct work_struct release_work;
    atomic_t released;
    + struct vfio_device *vfio_device;
    } vdev;
    #endif
    +
    + struct list_head dmabuf_obj_list_head;
    + struct mutex dmabuf_lock;
    + struct idr object_idr;
    +
    + struct completion vblank_done;
    +
    };

    /* validating GM healthy status*/
    @@ -543,6 +552,8 @@ struct intel_gvt_ops {
    const char *name);
    bool (*get_gvt_attrs)(struct attribute ***type_attrs,
    struct attribute_group ***intel_vgpu_type_groups);
    + int (*vgpu_query_plane)(struct intel_vgpu *vgpu, void *);
    + int (*vgpu_get_dmabuf)(struct intel_vgpu *vgpu, unsigned int);
    };


    diff --git a/drivers/gpu/drm/i915/gvt/hypercall.h b/drivers/gpu/drm/i915/gvt/hypercall.h
    index 32c345c..a1bd82f 100644
    --- a/drivers/gpu/drm/i915/gvt/hypercall.h
    +++ b/drivers/gpu/drm/i915/gvt/hypercall.h
    @@ -56,6 +56,8 @@ struct intel_gvt_mpt {
    int (*set_trap_area)(unsigned long handle, u64 start, u64 end,
    bool map);
    int (*set_opregion)(void *vgpu);
    + int (*get_vfio_device)(void *vgpu);
    + void (*put_vfio_device)(void *vgpu);
    };

    extern struct intel_gvt_mpt xengt_mpt;
    diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
    index 7875bc0..5cc166c 100644
    --- a/drivers/gpu/drm/i915/gvt/kvmgt.c
    +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
    @@ -378,10 +378,23 @@ static int intel_vgpu_register_reg(struct intel_vgpu *vgpu,
    vgpu->vdev.region[vgpu->vdev.num_regions].flags = flags;
    vgpu->vdev.region[vgpu->vdev.num_regions].data = data;
    vgpu->vdev.num_regions++;
    + return 0;
    +}
    +
    +static int kvmgt_get_vfio_device(void *p_vgpu)
    +{
    + struct intel_vgpu *vgpu = (struct intel_vgpu *)p_vgpu;

    + vgpu->vdev.vfio_device = vfio_device_get_from_dev(
    + mdev_dev(vgpu->vdev.mdev));
    + if (!vgpu->vdev.vfio_device) {
    + gvt_vgpu_err("failed to get vfio device\n");
    + return -ENODEV;
    + }
    return 0;
    }

    +
    static int kvmgt_set_opregion(void *p_vgpu)
    {
    struct intel_vgpu *vgpu = (struct intel_vgpu *)p_vgpu;
    @@ -408,6 +421,14 @@ static int kvmgt_set_opregion(void *p_vgpu)
    return ret;
    }

    +static void kvmgt_put_vfio_device(void *vgpu)
    +{
    + if (WARN_ON(!((struct intel_vgpu *)vgpu)->vdev.vfio_device))
    + return;
    +
    + vfio_device_put(((struct intel_vgpu *)vgpu)->vdev.vfio_device);
    +}
    +
    static int intel_vgpu_create(struct kobject *kobj, struct mdev_device *mdev)
    {
    struct intel_vgpu *vgpu = NULL;
    @@ -1142,6 +1163,33 @@ static long intel_vgpu_ioctl(struct mdev_device *mdev, unsigned int cmd,
    } else if (cmd == VFIO_DEVICE_RESET) {
    intel_gvt_ops->vgpu_reset(vgpu);
    return 0;
    + } else if (cmd == VFIO_DEVICE_QUERY_GFX_PLANE) {
    + struct vfio_device_gfx_plane_info dmabuf;
    + int ret = 0;
    +
    + minsz = offsetofend(struct vfio_device_gfx_plane_info,
    + dmabuf_id);
    + if (copy_from_user(&dmabuf, (void __user *)arg, minsz))
    + return -EFAULT;
    + if (dmabuf.argsz < minsz)
    + return -EINVAL;
    +
    + ret = intel_gvt_ops->vgpu_query_plane(vgpu, &dmabuf);
    + if (ret != 0)
    + return ret;
    +
    + return copy_to_user((void __user *)arg, &dmabuf, minsz) ?
    + -EFAULT : 0;
    + } else if (cmd == VFIO_DEVICE_GET_GFX_DMABUF) {
    + __u32 dmabuf_id;
    + __s32 dmabuf_fd;
    +
    + if (get_user(dmabuf_id, (__u32 __user *)arg))
    + return -EFAULT;
    +
    + dmabuf_fd = intel_gvt_ops->vgpu_get_dmabuf(vgpu, dmabuf_id);
    + return dmabuf_fd;
    +
    }

    return 0;
    @@ -1383,6 +1431,9 @@ static int kvmgt_guest_init(struct mdev_device *mdev)
    kvmgt_protect_table_init(info);
    gvt_cache_init(vgpu);

    + mutex_init(&vgpu->dmabuf_lock);
    + init_completion(&vgpu->vblank_done);
    +
    info->track_node.track_write = kvmgt_page_track_write;
    info->track_node.track_flush_slot = kvmgt_page_track_flush_slot;
    kvm_page_track_register_notifier(kvm, &info->track_node);
    @@ -1524,6 +1575,8 @@ struct intel_gvt_mpt kvmgt_mpt = {
    .write_gpa = kvmgt_write_gpa,
    .gfn_to_mfn = kvmgt_gfn_to_pfn,
    .set_opregion = kvmgt_set_opregion,
    + .get_vfio_device = kvmgt_get_vfio_device,
    + .put_vfio_device = kvmgt_put_vfio_device,
    };
    EXPORT_SYMBOL_GPL(kvmgt_mpt);

    diff --git a/drivers/gpu/drm/i915/gvt/mpt.h b/drivers/gpu/drm/i915/gvt/mpt.h
    index c99e796..ca8005a 100644
    --- a/drivers/gpu/drm/i915/gvt/mpt.h
    +++ b/drivers/gpu/drm/i915/gvt/mpt.h
    @@ -309,4 +309,34 @@ static inline int intel_gvt_hypervisor_set_opregion(struct intel_vgpu *vgpu)
    return intel_gvt_host.mpt->set_opregion(vgpu);
    }

    +/**
    + * intel_gvt_hypervisor_get_vfio_device - increase vfio device ref count
    + * @vgpu: a vGPU
    + *
    + * Returns:
    + * Zero on success, negative error code if failed.
    + */
    +static inline int intel_gvt_hypervisor_get_vfio_device(struct intel_vgpu *vgpu)
    +{
    + if (!intel_gvt_host.mpt->get_vfio_device)
    + return 0;
    +
    + return intel_gvt_host.mpt->get_vfio_device(vgpu);
    +}
    +
    +/**
    + * intel_gvt_hypervisor_put_vfio_device - decrease vfio device ref count
    + * @vgpu: a vGPU
    + *
    + * Returns:
    + * Zero on success, negative error code if failed.
    + */
    +static inline void intel_gvt_hypervisor_put_vfio_device(struct intel_vgpu *vgpu)
    +{
    + if (!intel_gvt_host.mpt->put_vfio_device)
    + return;
    +
    + intel_gvt_host.mpt->put_vfio_device(vgpu);
    +}
    +
    #endif /* _GVT_MPT_H_ */
    diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
    index 42aee6b..b964848 100644
    --- a/drivers/gpu/drm/i915/gvt/vgpu.c
    +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
    @@ -236,6 +236,7 @@ void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu)
    }

    intel_vgpu_stop_schedule(vgpu);
    + intel_vgpu_dmabuf_cleanup(vgpu);

    mutex_unlock(&gvt->lock);
    }
    @@ -265,6 +266,7 @@ void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
    intel_gvt_hypervisor_detach_vgpu(vgpu);
    intel_vgpu_free_resource(vgpu);
    intel_vgpu_clean_mmio(vgpu);
    + intel_vgpu_dmabuf_cleanup(vgpu);
    vfree(vgpu);

    intel_gvt_update_vgpu_types(gvt);
    @@ -349,7 +351,8 @@ static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt,
    vgpu->handle = param->handle;
    vgpu->gvt = gvt;
    vgpu->sched_ctl.weight = param->weight;
    -
    + INIT_LIST_HEAD(&vgpu->dmabuf_obj_list_head);
    + idr_init(&vgpu->object_idr);
    intel_vgpu_init_cfg_space(vgpu, param->primary);

    ret = intel_vgpu_init_mmio(vgpu);
    diff --git a/drivers/gpu/drm/i915/i915_gem_object.h b/drivers/gpu/drm/i915/i915_gem_object.h
    index 63ce38c..3773155 100644
    --- a/drivers/gpu/drm/i915/i915_gem_object.h
    +++ b/drivers/gpu/drm/i915/i915_gem_object.h
    @@ -260,6 +260,8 @@ struct drm_i915_gem_object {
    } userptr;

    unsigned long scratch;
    +
    + void *gvt_info;
    };

    /** for phys allocated objects */
    --
    2.7.4
    \
     
     \ /
      Last update: 2017-11-15 10:20    [W:4.135 / U:0.080 seconds]
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