lkml.org 
[lkml]   [2017]   [Oct]   [8]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 2/6] ARM: sun8i: r40: add USB host port nodes for R40
    Date
    From: Icenowy Zheng <icenowy@aosc.xyz>

    Allwinner R40 SoC features a USB OTG port and two USB HOST ports.

    Add support for the host ports in the DTSI file.

    The OTG controller still cannot work with existing compatibles, and needs
    more investigation. So it's not added yet.

    Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
    ---
    arch/arm/boot/dts/sun8i-r40.dtsi | 78 ++++++++++++++++++++++++++++++++++++++++
    1 file changed, 78 insertions(+)

    diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
    index d5a6745409ae..f6c917cbbaac 100644
    --- a/arch/arm/boot/dts/sun8i-r40.dtsi
    +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
    @@ -173,6 +173,84 @@
    #size-cells = <0>;
    };

    + usbphy: phy@1c13400 {
    + compatible = "allwinner,sun8i-r40-usb-phy";
    + reg = <0x01c13400 0x14>,
    + <0x01c14800 0x4>,
    + <0x01c19800 0x4>,
    + <0x01c1c800 0x4>;
    + reg-names = "phy_ctrl",
    + "pmu0",
    + "pmu1",
    + "pmu2";
    + clocks = <&ccu CLK_USB_PHY0>,
    + <&ccu CLK_USB_PHY1>,
    + <&ccu CLK_USB_PHY2>;
    + clock-names = "usb0_phy",
    + "usb1_phy",
    + "usb2_phy";
    + resets = <&ccu RST_USB_PHY0>,
    + <&ccu RST_USB_PHY1>,
    + <&ccu RST_USB_PHY2>;
    + reset-names = "usb0_reset",
    + "usb1_reset",
    + "usb2_reset";
    + status = "disabled";
    + #phy-cells = <1>;
    + };
    +
    + ehci1: usb@1c19000 {
    + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
    + reg = <0x01c19000 0x100>;
    + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
    + clocks = <&ccu CLK_BUS_OHCI1>,
    + <&ccu CLK_BUS_EHCI1>,
    + <&ccu CLK_USB_OHCI1>;
    + resets = <&ccu RST_BUS_OHCI1>,
    + <&ccu RST_BUS_EHCI1>;
    + phys = <&usbphy 1>;
    + phy-names = "usb";
    + status = "disabled";
    + };
    +
    + ohci1: usb@1c19400 {
    + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
    + reg = <0x01c19400 0x100>;
    + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
    + clocks = <&ccu CLK_BUS_OHCI1>,
    + <&ccu CLK_USB_OHCI1>;
    + resets = <&ccu RST_BUS_OHCI1>;
    + phys = <&usbphy 1>;
    + phy-names = "usb";
    + status = "disabled";
    + };
    +
    + ehci2: usb@1c1c000 {
    + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
    + reg = <0x01c1c000 0x100>;
    + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
    + clocks = <&ccu CLK_BUS_OHCI2>,
    + <&ccu CLK_BUS_EHCI2>,
    + <&ccu CLK_USB_OHCI2>;
    + resets = <&ccu RST_BUS_OHCI2>,
    + <&ccu RST_BUS_EHCI2>;
    + phys = <&usbphy 2>;
    + phy-names = "usb";
    + status = "disabled";
    + };
    +
    + ohci2: usb@1c1c400 {
    + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
    + reg = <0x01c1c400 0x100>;
    + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
    + clocks = <&ccu CLK_BUS_OHCI2>,
    + <&ccu CLK_USB_OHCI2>;
    + resets = <&ccu RST_BUS_OHCI2>;
    + phys = <&usbphy 2>;
    + phy-names = "usb";
    + status = "disabled";
    + };
    +
    ccu: clock@1c20000 {
    compatible = "allwinner,sun8i-r40-ccu";
    reg = <0x01c20000 0x400>;
    --
    2.13.6
    \
     
     \ /
      Last update: 2017-10-08 06:32    [W:4.147 / U:0.080 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site